Semiconductor device structure and methods of forming the same
US-2025366169-A1 · Nov 27, 2025 · US
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Hsieh Ping-Pang patents
Hsieh Ping-Pang is listed as an inventor on 39 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hsieh Ping-Pang |
| Total patents | 39 |
| First publication | Mar 17, 2015 |
| Latest publication | Nov 27, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Polysilicon Removal In Word Line Contact Region Of Memory Devices
US-2025324589-A1 · Oct 16, 2025 · US
Polysilicon removal in word line contact region of memory devices
US-12376297-B2 · Jul 29, 2025 · US
Semiconductor device structure and methods of forming the same
US-2025089350-A1 · Mar 13, 2025 · US
Polysilicon removal in word line contact region of memory devices
US-12041771-B2 · Jul 16, 2024 · US
Polysilicon Removal In Word Line Contact Region Of Memory Devices
US-2023389309-A1 · Nov 30, 2023 · US
Floating gate isolation
US-11581441-B2 · Feb 14, 2023 · US
Polysilicon removal in word line contact region of memory devices
US-11527543-B2 · Dec 13, 2022 · US
Polysilicon removal in word line contact region of memory devices
US-2022367495-A1 · Nov 17, 2022 · US
Methods for improving interlayer dielectric layer topography
US-11257719-B2 · Feb 22, 2022 · US
Recent patents
Latest publications not already listed above.
Polysilicon removal in word line contact region of memory devices
US-2021408023-A1 · Dec 30, 2021 · US
Floating gate isolation
US-2021043774-A1 · Feb 11, 2021 · US
Floating gate isolation and method for manufacturing the same
US-10818804-B2 · Oct 27, 2020 · US
Methods for Improving Interlayer Dielectric Layer Topography
US-2020294862-A1 · Sep 17, 2020 · US
Methods for improving interlayer dielectric layer topography
US-10699960-B2 · Jun 30, 2020 · US
Formation of semiconductor device with resistors having different resistances
US-10629593-B2 · Apr 21, 2020 · US
Methods for Improving Interlayer Dielectric Layer Topography
US-2020006152-A1 · Jan 2, 2020 · US
Apparatus and method for memory device
US-10164073-B2 · Dec 25, 2018 · US
Method for forming semiconductor device structure
US-10141401-B2 · Nov 27, 2018 · US
Gate structure with multiple spacers
US-10103235-B2 · Oct 16, 2018 · US
Method for forming semiconductor device structure
US-2017263464-A1 · Sep 14, 2017 · US
Gate structure with multiple spacers
US-2017243946-A1 · Aug 24, 2017 · US
Silicide process using OD spacers
US-9711657-B2 · Jul 18, 2017 · US
Semiconductor device structure and method for forming the same
US-9666668-B2 · May 30, 2017 · US
Gate structure with multiple spacer and method for manufacturing the same
US-9653302-B2 · May 16, 2017 · US
Floating gate isolation and method for manufacturing the same
US-2017125602-A1 · May 4, 2017 · US
Semiconductor device structure and method for forming the same
US-2017117355-A1 · Apr 27, 2017 · US
Gate structure with multiple spacer and method for manufacturing the same
US-2017032971-A1 · Feb 2, 2017 · US
Formation of semiconductor device with resistors
US-2016233215-A1 · Aug 11, 2016 · US
Memory device structure and method
US-9406519-B2 · Aug 2, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 36 |
| Taiwan Semiconductor Mfg | 5 |
| Hsieh Ping-Pang | 2 |
| Chuang Kun-Tsang | 1 |
| Huang Chia Hsing | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/0411 | 23 |
| H01L29/66825 | 20 |
| H10D30/6891 | 18 |
| H10D64/035 | 16 |
| H10B41/30 | 14 |