Polysilicon Removal In Word Line Contact Region Of Memory Devices

Patent metadata

Field	Value
Publication number	US-2023389309-A1
Application number	US-202318447965-A
Country	US
Kind code	A1
Filing date	Aug 10, 2023
Priority date	Jun 30, 2020
Publication date	Nov 30, 2023
Grant date	—

Abstract

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

First claim

What is claimed is:

1 . A structure, comprising:
a substrate; a first polysilicon line and a second polysilicon line parallel to each other disposed on the substrate with each of the first and second polysilicon lines comprising a contact region and a non-contact region, wherein the contact region is wider than the non-contact region; a first polysilicon layer disposed on a sidewall of the non-contact region of the first polysilicon line; a second polysilicon layer disposed on a sidewall of the non-contact region of the second polysilicon line; a first space between the first and second polysilicon layers; and a second space between the contact regions of the first and second polysilicon layers.

2 . The structure of claim 1 , wherein the second space has an aspect ratio between about 1 and about 2.4.

3 . The structure of claim 1 , wherein bottom surfaces of the first and second spaces are polysilicon layer free.

4 . The structure of claim 1 , wherein the contact region of the second polysilicon line comprises a control gate and one or more floating gates.

5 . The structure of claim 1 , wherein the non-contact region of the second polysilicon line comprises a control gate and a floating gate.

6 . The structure of claim 5 , further comprising a nitride layer between the control gate and the floating gate.

7 . The structure of claim 1 , further comprising a contact disposed on the contact region of the second polysilicon line.

8 . The structure of claim 1 , further comprising a contact disposed between the non-contact region of the first polysilicon line and the non-contact region of the second polysilicon line.

9 . A semiconductor device, comprising:
a dielectric layer on a substrate; first and second gate structures on the dielectric layer, wherein each of the first and second gate structures comprises a non-contact region and a contact region wider than the non-contact region; a first polysilicon layer disposed on a sidewall of the non-contact region of the first gate structure; a second polysilicon layer disposed on a sidewall of the non-contact region of the second gate structure; a contact between the first and second polysilicon layers, wherein the contact is electrically coupled to source/drain regions of the substrate; and a dielectric structure on the dielectric layer and between the contact regions of the first and second gate structures.

10 . The semiconductor device of claim 9 , wherein the dielectric structure has an aspect ratio between about 1 and about 2.4.

11 . The semiconductor device of claim 9 , wherein the dielectric structure is in contact with the dielectric layer to separate the first gate structure from the second gate structure.

12 . The semiconductor device of claim 9 , wherein the contact region of the second gate structure comprises a control gate above the dielectric layer and one or more floating gates between the control gate and the dielectric layer.

13 . The semiconductor device of claim 12 , further comprising an additional contact connected to the contact region of the second gate structure, wherein the additional contact is in contact with the control gate.

14 . The semiconductor device of claim 9 , wherein the non-contact region of the second gate structure comprises a control gate above the dielectric layer and a floating gate between the control gate and the dielectric layer.

15 . The semiconductor device of claim 14 , further comprising a nitride layer between the control gate and the floating gate.

16 . A semiconductor structure, comprising:
a dielectric layer on a substrate; a first polysilicon line comprising a first contact region and a first non-contact region on the dielectric layer; a second polysilicon line parallel to the first polysilicon line and on the dielectric layer, wherein the second polysilicon line comprises a second contact region and a second non-contact region; a first polysilicon layer disposed on a sidewall of the first non-contact region; a second polysilicon layer disposed on a sidewall of the second non-contact region; and a contact between the first and second polysilicon layers, wherein the contact extends through the dielectric layer into the substrate.

17 . The semiconductor structure of claim 16 , wherein the second non-contact region of the second polysilicon line comprises a control gate and a floating gate on the dielectric layer.

18 . The semiconductor device of claim 17 , further comprising a nitride layer surrounding the control gate.

19 . The semiconductor structure of claim 16 , wherein the second contact region of the second polysilicon line comprises a control gate and one or more floating gates on the dielectric layer.

20 . The semiconductor structure of claim 19 , further comprising an additional contact disposed on the second contact region of the second polysilicon line, wherein the additional contact is in contact with the control gate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Yen-Jou
• Lin Hsin-Hui
• Wang Yu-Liang
• Lee Chih-Ming
• Liao Keng-Ying
• Hsieh Ping-Pang
• Yeh Su-Yu

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title