Polysilicon removal in word line contact region of memory devices

Patent metadata

Field	Value
Publication number	US-12041771-B2
Application number	US-202217815043-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Jun 30, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

First claim

What is claimed is:

1. A structure, comprising:
a substrate;
a first polysilicon line and a second polysilicon line parallel to each other disposed on the substrate with each of the first and second polysilicon lines comprising a contact region and a non-contact region, wherein each contact region is wider than each non-contact region and wherein the contact region of the first polysilicon line is offset with respect to the contact region of the second polysilicon line;
a polysilicon layer disposed on a sidewall of the non-contact region of the first polysilicon line and opposite to the contact region of the second polysilicon line;
a space between the polysilicon layer and the contact region of the second polysilicon line; and
a contact disposed on the contact region of the second polysilicon line.

2. The structure of claim 1 , wherein the space has an aspect ratio between about 1 and about 2.4.

3. The structure of claim 1 , wherein a dielectric layer is disposed in the space and a bottom surface of the space is polysilicon layer free.

4. The structure of claim 1 , wherein the contact region of the second polysilicon line comprises a control gate and one or more floating gates.

5. The structure of claim 4 , wherein the contact is in contact with the control gate.

6. The structure of claim 4 , further comprising a nitride layer isolating the control gate from the one or more floating gates.

7. The structure of claim 1 , wherein an offset distance between adjacent contact regions of the first and second polysilicon lines is greater than a spacing between the contact region of the second polysilicon line and the non-contact region of the first polysilicon line.

8. A semiconductor device, comprising:
a dielectric layer on a substrate;
first and second gate structures on the dielectric layer, wherein each of the first and second gate structures comprises a non-contact region and a contact region wider than the non-contact region, and wherein the contact region of the first gate structure is adjacent to the non-contact region of the second gate structure;
a polysilicon layer disposed on a sidewall of the non-contact region of the first gate structure; and
a dielectric structure on the dielectric layer and between the polysilicon layer and the contact region of the second gate structure.

9. The semiconductor device of claim 8 , wherein the dielectric structure has an aspect ratio between about 1 and about 2.4.

10. The semiconductor device of claim 8 , wherein the dielectric structure is in contact with the dielectric layer to separate the first gate structure from the contact region of the second gate structure.

11. The semiconductor device of claim 8 , wherein the contact region of the second gate structure comprises a control gate above the dielectric layer and one or more floating gates between the control gate and the dielectric layer.

12. The semiconductor device of claim 11 , further comprising an erase gate adjacent to the control gate and the one or more floating gates.

13. The semiconductor device of claim 11 , further comprising a contact disposed on the contact region of the second gate structure, wherein the contact is in contact with the control gate.

14. The semiconductor device of claim 11 , further comprising a nitride layer between the control gate and the one or more floating gates.

15. A semiconductor structure, comprising:
a dielectric layer on a substrate;
a first polysilicon line comprising a first contact region and a first non-contact region on the dielectric layer;
a second polysilicon line parallel to the first polysilicon line and on the dielectric layer, wherein the second polysilicon line comprises a second contact region and a second non-contact region, and wherein the second contact region is opposite to the first non-contact region;
a first polysilicon layer disposed on a sidewall of the first non-contact region;
a second polysilicon layer disposed on a sidewall of the second contact region; and
a dielectric structure on the dielectric layer and between the first and second polysilicon layers.

16. The semiconductor structure of claim 15 , wherein the dielectric structure is in contact with the dielectric layer and separates the first polysilicon layer from the second polysilicon layer.

17. The semiconductor structure of claim 15 , wherein the second contact region of the second polysilicon line comprises a control gate and one or more floating gates on the dielectric layer.

18. The semiconductor structure of claim 17 , further comprising a contact disposed on the second contact region of the second polysilicon line, wherein the contact is in contact with the control gate.

19. The semiconductor structure of claim 17 , further comprising a nitride layer separating the control gate from the one or more floating gates.

20. The semiconductor structure of claim 17 , further comprising an erase gate adjacent to the control gate and the one or more floating gates.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Yen-Jou
• Lee Chih-Ming
• Liao Keng-Ying
• Hsieh Ping-Pang
• Yeh Su-Yu
• Lin Hsin-Hui
• Wang Yu-Liang

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title