Floating gate isolation and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017125602-A1
Application number	US-201514925551-A
Country	US
Kind code	A1
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

First claim

1 . A semiconductor device, comprising:
a substrate; a tunneling oxide layer disposed on the substrate; a floating gate disposed on the tunneling oxide layer; an isolation layer covering a top of the floating gate and peripherally enclosing the tunneling oxide layer and the floating gate; and a control gate disposed over a top of the isolation layer.

2 . The semiconductor device of claim 1 , wherein the floating gate comprises a polysilicon layer.

3 . The semiconductor device of claim 1 , wherein the isolation layer comprises a multi-layered structure.

4 . The semiconductor device of claim 1 ,
wherein the isolation layer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.

5 . The semiconductor device of claim 1 , wherein the control gate comprises a polysilicon layer.

6 . A semiconductor device, comprising:
a substrate having at least two active regions defined by at least one isolation structure disposed in the substrate; at least two gate structures respectively disposed on the active regions, wherein each of the gate structures comprises:
a tunneling oxide layer disposed on the active region and a first portion of the at least one isolation structure;
a floating gate disposed on the tunneling oxide layer; and
an isolation layer covering a top of the floating gate and peripherally enclosing the tunneling oxide layer and the floating gate; and
a control gate extending on the isolation layers and a second portion of the at least one isolation structure between the gate structures.

7 . The semiconductor device of claim 6 , wherein the at least one isolation structure comprises a shallow trench isolation structure.

8 . The semiconductor device of claim 6 , wherein each of the floating gate comprises a polysilicon layer.

9 . The semiconductor device of claim 6 , wherein each of the isolation layer comprises a multi-layered structure.

10 . The semiconductor device of claim 6 ,
wherein each of the isolation layer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.

11 . The semiconductor device of claim 6 , wherein the control gate comprises a polysilicon layer.

12 . A method for manufacturing a semiconductor device, comprising:
providing a substrate; forming at least one tunneling oxide layer on the substrate; forming at least one floating gate on the at least one tunneling oxide layer; forming at least one isolation layer covering a top of the at least one floating gate and peripherally enclosing the at least one tunneling oxide layer and the at least one floating gate; and forming a control gate over a top of the at least one isolation layer.

13 . The method of claim 12 , wherein forming the at least one tunneling oxide layer and forming the at least one floating gate comprise:
forming an oxide layer blanketly covering the substrate; forming a conductive layer blanketly covering the oxide layer; and removing a portion of the conductive layer and a portion of the oxide layer to respectively form the at least one floating gate and the at least one tunneling oxide layer.

14 . The method of claim 12 , wherein forming the at least one floating gate comprising forming the at least one floating gate from polysilicon.

15 . The method of claim 12 , wherein forming the at least one isolation layer comprises forming the at least one isolation layer comprising a multi-layered structure.

16 . The method of claim 12 , wherein forming the at least one isolation layer comprises forming the at least one isolation layer comprising an oxide-nitride-oxide (ONO) structure.

17 . The method of claim 12 , wherein forming the control gate comprises forming the control gate from polysilicon.

18 . The method of claim 12 , wherein providing the substrate comprises providing the substrate having a plurality of active regions defined by at least one isolation structure which is disposed in the substrate.

19 . The method of claim 18 , wherein
the number of the at least one tunneling oxide layer is more than one, and forming the tunneling oxide layers is performed to form the tunneling oxide layers respectively on the active regions and a first portion of the at least one isolation structure; the number of the at least one floating gate is more than one, and forming the floating gates is performed to form the floating gates respectively on the tunneling oxide layers; the number of the at least one isolation layer is more than one, and forming the isolation layers is performed to form the isolation layers respectively covering the floating gates and peripherally enclosing the tunneling oxide layers and the floating gates; and forming the control gate is performed to form the control gate extending on the isolation layers and a second portion of the at least one isolation structure between the tunneling oxide layers.

20 . The method of claim 18 , wherein the at least one isolation structure comprises a shallow trench isolation structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• HSU Shih-Lu
• Hsieh Ping-Pang
• LU Szu-Hsien
• Lin Yu-Chu

Classifications

• H01L29/7883 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6891 Primary

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title