Semiconductor device structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2025366169-A1
Application number	US-202519292914-A
Country	US
Kind code	A1
Filing date	Aug 7, 2025
Priority date	Sep 13, 2023
Publication date	Nov 27, 2025
Grant date	—

Abstract

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

First claim

1 . A semiconductor device structure, comprising:
a first gate structure disposed over a substrate in an active device region; an insulating material disposed over the substrate in a passive device region; a second gate structure disposed over the insulating material in the passive device region; a resistor structure disposed over the insulating material and adjacent the second gate structure in the passive device region; a first conductive contact electrically connected to the second gate structure; a tuning electrode disposed over the resistor structure; and a dielectric layer disposed between the tuning electrode and the resistor structure, wherein the tuning electrode is electrically insulated from the resistor structure by the dielectric layer.

2 . The semiconductor device structure of claim 1 , further comprising a third gate structure disposed over the insulating material, wherein the resistor structure is disposed between the second and third gate structures.

3 . The semiconductor device structure of claim 2 , further comprising a second conductive contact electrically connected to the third gate structure.

4 . The semiconductor device structure of claim 3 , wherein each of the first and second conductive contacts comprises a seed layer and a conductive material.

5 . The semiconductor device structure of claim 1 , wherein the resistor structure comprises a semiconductor material.

6 . The semiconductor device structure of claim 5 , wherein the dielectric layer comprises an oxide.

7 . The semiconductor device structure of claim 6 , wherein the dielectric layer is a conformal layer.

8 . The semiconductor device structure of claim 2 , further comprising:
first spacers disposed over the substrate in the active device region, wherein the first gate structure is disposed between the first spacers; and second spacers disposed over the insulating material in the passive device region, wherein the second and third gate structures and the resistor structure are disposed between the second spacers.

9 . A semiconductor device structure, comprising:
an insulating material disposed over a substrate; a resistor structure disposed over the insulating material; first and second spacers disposed over the insulating material, wherein the resistor structure is disposed between the first and second spacers; a first conductive contact electrically connected to the resistor structure; a first tuning electrode extending into the resistor structure; and a first dielectric layer disposed between the first tuning electrode and the resistor structure, wherein the first tuning electrode is electrically insulated from the resistor structure by the first dielectric layer.

10 . The semiconductor device structure of claim 9 , wherein the first dielectric layer is a conformal layer and extends into the resistor structure.

11 . The semiconductor device structure of claim 10 , further comprising a second tuning electrode and a second dielectric layer extending into the resistor structure.

12 . The semiconductor device structure of claim 11 , wherein the first and second tuning electrodes extend into the resistor structure at a same depth.

13 . The semiconductor device structure of claim 11 , wherein the first and second tuning electrodes extend into the resistor structure at a different depths.

14 . The semiconductor device structure of claim 9 , wherein the first tuning electrode extends through the resistor structure.

15 . The semiconductor device structure of claim 9 , further comprising a first gate structure and a second gate structure disposed over the insulating material, wherein the resistor structure is disposed between the first and second gate structures.

16 . A method, comprising:
depositing a semiconductor material in an active device region and a passive device region; patterning the semiconductor material to form a sacrificial gate electrode in the active device region and a resistor structure in the passive device region; replacing the sacrificial gate electrode with a gate structure in the active device region; forming a dielectric layer over the semiconductor material in the passive device region; and forming a tuning electrode on the dielectric layer.

17 . The method of claim 16 , wherein the forming of the dielectric layer comprises:
depositing an interlayer dielectric layer over the semiconductor material; and forming a first opening in the interlayer dielectric layer to expose the semiconductor material in the passive device region, wherein the dielectric layer is formed in the first opening.

18 . The method of claim 17 , wherein the tuning electrode is formed in the first opening.

19 . The method of claim 17 , further comprising forming a second opening in the interlayer dielectric layer, wherein the dielectric layer is formed in the second opening.

20 . The method of claim 19 , further comprising removing the dielectric layer in the second opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Chieh-Ning
• Ting Nai-Hsin
• Kuo Fang-Ting
• Hsieh Ping-Pang

Classifications

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/023

  having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031) · CPC title

• H10D1/474

  comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides · CPC title

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title