Polysilicon Removal In Word Line Contact Region Of Memory Devices

Patent metadata

Field	Value
Publication number	US-2025324589-A1
Application number	US-202519250367-A
Country	US
Kind code	A1
Filing date	Jun 26, 2025
Priority date	Jun 30, 2020
Publication date	Oct 16, 2025
Grant date	—

Abstract

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

First claim

What is claimed is:

1 . A method, comprising:
forming, on a substrate, a first polysilicon line and a second polysilicon line, wherein the first and second polysilicon lines are spaced apart by a polysilicon layer and the second polysilicon line comprises a contact region; depositing a mask layer on the first polysilicon line, the contact region of the second polysilicon line, and the polysilicon layer; removing a portion of the mask layer to expose a first portion of the polysilicon layer with a first etching process, wherein unremoved portions of the mask layer remain on the polysilicon layer; removing the unremoved portions of the mask layer with a second etching process to expose a second portion of the polysilicon layer larger than the first portion; and removing the exposed second portion of the polysilicon layer to form a spacing between the contact region of the second polysilicon line and the first polysilicon line.

2 . The method of claim 1 , wherein removing the portion of the mask layer comprises:
removing a nitride masking layer disposed on an oxide masking layer, wherein the oxide masking layer is disposed on the polysilicon layer; and removing a portion the oxide masking layer disposed on the polysilicon layer adjacent to the contact region of the second polysilicon line.

3 . The method of claim 1 , wherein removing the unremoved portions of the mask layer comprises etching an oxide masking layer disposed on the first polysilicon line, the contact region of the second polysilicon line, and the polysilicon layer.

4 . The method of claim 1 , wherein depositing the mask layer comprises covering, with the mask layer, sidewall and bottom surfaces of a divot formed on a top surface of the polysilicon layer.

5 . The method of claim 1 , wherein removing the portion of the mask layer comprises patterning a photoresist layer on the mask layer to expose an area of the mask layer over the polysilicon layer, wherein the exposed area of the mask layer is narrower than the polysilicon layer.

6 . The method of claim 1 , wherein removing the unremoved portions of the mask layer comprises forming an undercut in un-etched portions of the mask layer.

7 . The method of claim 1 , wherein depositing the mask layer comprises:
depositing an oxide layer on the first polysilicon line, the contact region of the second polysilicon line, and the polysilicon layer; and depositing a nitride layer on the oxide layer.

8 . A method, comprising:
forming a first hard mask layer and a second hard mask layer in a divot on a top portion of a polysilicon layer, wherein the polysilicon layer is interposed between a first polysilicon gate structure and a second polysilicon gate structure, and wherein the first and second hard mask layers cover a sidewall surface and a bottom surface of the divot; etching the first and second hard mask layers in the divot with a first etching process, wherein a portion of the first hard mask layer remains on the sidewall and bottom surfaces of the divot; removing the portion of the first hard mask layer from the sidewall and bottom surfaces of the divot with a second etching process; and removing the polysilicon layer under the divot to form a separation between the first polysilicon gate structure and the second polysilicon gate structure.

9 . The method of claim 8 , further comprising forming a contact on the second polysilicon gate structure.

10 . The method of claim 8 , wherein forming the first hard mask layer comprises depositing an oxide layer on the top portion of the polysilicon layer.

11 . The method of claim 8 , wherein forming the second hard mask layer comprises depositing a nitride layer on the first hard mask layer.

12 . The method of claim 8 , wherein etching the first and second hard mask layers in the divot comprises performing an etch with difluoromethane (CH 2 F 2 ), sulfur hexafluoride (SF 6 ), helium (He), and nitrogen (N 2 ).

13 . The method of claim 8 , wherein etching the first and second hard mask layers in the divot comprises using an etching chemistry comprising a nitrogen flow between about 20 sccm and about 100 sccm for a silicon-to-nitride etching selectivity of about 1 to about 6.

14 . The method of claim 8 , wherein removing the portion of the first hard mask layer comprises performing a wet etching process with diluted hydrofluoric acid (HF) for about 20 seconds.

15 . The method of claim 8 , wherein removing the polysilicon layer under the divot comprises performing a dry etching process selective to polysilicon.

16 . The method of claim 8 , wherein removing the polysilicon layer under the divot comprises forming the separation narrower than a distance between first and the second polysilicon gate structures.

17 . A method, comprising:
forming, on a substrate, first and second gate structures separated by a polysilicon layer, wherein the polysilicon layer comprises a divot between the first gate structure and a contact region of the second gate structure; forming a mask layer on the first gate structure, the second gate structure, and the polysilicon layer; removing a portion of the mask layer to expose a sidewall surface and a bottom surface of the divot on the polysilicon layer; and removing the polysilicon layer under the divot to form a separation between the first gate structure and the second gate structure.

18 . The method of claim 17 , wherein the forming the mask layer comprises depositing a hard mask layer on the sidewall and bottom surfaces of the divot.

19 . The method of claim 17 , wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer, and wherein the removing the portion of the mask layer comprises:
etching the first mask layer with a dry etching process; and etching the second mask layer with a wet etching process.

20 . The method of claim 17 , wherein removing the portion of the mask layer comprises forming an undercut in un-etched portions of the mask layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Yen-Jou
• Lin Hsin-Hui
• Wang Yu-Liang
• Lee Chih-Ming
• Liao Keng-Ying
• Hsieh Ping-Pang
• Yeh Su-Yu

Classifications

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title