Gate structure with multiple spacers

Patent metadata

Field	Value
Publication number	US-10103235-B2
Application number	US-201715592329-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	Jul 31, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a floating gate structure formed over the substrate;
a dielectric structure formed over the floating gate structure;
a control gate structure formed over the dielectric structure;
a first spacer formed over a lower portion of a sidewall of the control gate structure; and
an upper spacer formed over a slope upper portion of the sidewall of the control gate structure,
wherein a portion of the control gate structure is in direct contact with the upper spacer.

2. The semiconductor structure as claimed in claim 1 , wherein a portion of the upper spacer overlaps with the first spacer.

3. The semiconductor structure as claimed in claim 1 , further comprising:
a second spacer formed over the first spacer and over a sidewall of the floating gate structure.

4. The semiconductor structure as claimed in claim 3 , further comprising:
a lower spacer formed over the second spacer and over a lower portion of the first spacer.

5. The semiconductor structure as claimed in claim 4 , wherein a portion of the lower spacer is in direct contact with the floating gate structure.

6. The semiconductor structure as claimed in claim 4 , further comprising:
a common source region formed adjacent to the lower spacer in the substrate; and
a contact formed over the common source region.

7. The semiconductor structure as claimed in claim 6 , further comprising:
a word line structure formed at a side of the floating gate structure opposite the contact.

8. A semiconductor structure, comprising:
a floating gate structure formed over a substrate;
a dielectric structure formed over the floating gate structure;
a control gate structure formed over the dielectric structure;
a first spacer formed over a sidewall of the control gate structure;
a second spacer formed over a sidewall of the floating gate structure;
a lower spacer formed over the second spacer; and
an upper spacer formed over the first spacer and extending onto the control gate structure,
wherein the upper spacer is in direct contact with the control gate structure, and the lower spacer is in direct contact with the floating gate structure.

9. The semiconductor structure as claimed in claim 8 , further comprising:
a common source region formed adjacent to the lower spacer in the substrate; and
a contact formed over the common source region.

10. The semiconductor structure as claimed in claim 8 , further comprising:
a cap structure formed over the control gate structure,
wherein the upper spacer further extends onto a sidewall of the cap structure.

11. The semiconductor structure as claimed in claim 8 , further comprising:
a word line structure formed over the substrate,
wherein the word line structure and the lower spacer are located at opposite sides of the floating gate structure.

12. A semiconductor structure, comprising:
a substrate;
a floating gate structure formed over the substrate;
a dielectric structure formed over the floating gate structure;
a control gate structure formed over the dielectric structure;
a first spacer formed over a lower portion of a sidewall of the control gate structure; and
an upper spacer formed over an upper portion of the sidewall of the control gate structure and vertically overlapping with the first spacer.

13. The semiconductor structure as claimed in claim 12 , wherein the control gate structure is in direct contact with the upper spacer.

14. The semiconductor structure as claimed in claim 12 , further comprising:
a second spacer formed over the first spacer and over a sidewall of the floating gate structure.

15. The semiconductor structure as claimed in claim 14 , further comprising:
a lower spacer overlapping with both the second spacer and the first spacer.

16. The semiconductor structure as claimed in claim 15 , wherein the lower spacer is in direct contact with the floating gate structure.

17. The semiconductor structure as claimed in claim 15 , further comprising:
a common source region formed adjacent to the lower spacer in the substrate; and
a contact formed over the common source region.

18. The semiconductor structure as claimed in claim 17 , further comprising:
a word line structure formed at a side of the floating gate structure opposite the contact.

19. The semiconductor structure as claimed in claim 17 , wherein the lower spacer covers a portion of the common source region.

20. The semiconductor structure as claimed in claim 1 , wherein the floating gate structure has a top portion and a bottom portion, and a width of the bottom portion of the floating gate structure is greater than a width of the top portion of the floating gate structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Chia-Ming
• Chuang Chiang-Ming
• Ho Pei-Chi
• Hsieh Ping-Pang

Classifications

• H01L29/788

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L29/42328 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic