Methods for improving interlayer dielectric layer topography

Patent metadata

Field	Value
Publication number	US-11257719-B2
Application number	US-202016889381-A
Country	US
Kind code	B2
Filing date	Jun 1, 2020
Priority date	Jun 27, 2018
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first gate structure having a first height disposed over a substrate in a first region;
a second gate structure having a second height disposed over the substrate in a second region, wherein the second height is less than the first height;
a first contact etch stop layer disposed over the first gate structure, wherein the first contact etch stop layer has a first thickness;
a second contact etch stop layer disposed over the second gate structure, wherein the second contact etch stop layer has a second thickness that is greater than the first thickness;
an interlayer dielectric layer disposed over the first contact etch stop layer and the second contact etch stop layer; and
wherein a difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

2. The integrated circuit device of claim 1 , wherein an interface area of the first region and the second region includes the second contact etch stop layer disposed over the first contact etch stop layer.

3. The integrated circuit device of claim 2 , wherein the interface area includes an isolation feature in the substrate, wherein the first contact etch stop layer and the second contact etch stop layer extend over the isolation feature.

4. The integrated circuit device of claim 1 , wherein a first material of the first contact etch stop layer is different than a second material of the second contact etch stop layer.

5. The integrated circuit device of claim 1 , wherein a first material of the first contact etch stop layer is the same as a second material of the second contact etch stop layer.

6. The integrated circuit device of claim 1 , wherein the second height is less than about 2,500 Å and the first height is greater than or equal to about 2,500 Å.

7. The integrated circuit device of claim 6 , wherein the first thickness is about 600 Å to about 700 Å and the second thickness is about 700 Å to about 850 Å.

8. The integrated circuit device of claim 1 , wherein the first contact etch stop layer is further disposed over the second gate structure and the second contact etch stop layer is disposed between the interlayer dielectric layer and the first contact etch stop layer.

9. An integrated circuit device comprising:
a first region of a wafer and a second region of the wafer;
a first contact etch stop layer disposed in the first region of the wafer;
a second contact etch stop layer disposed in the second region of the wafer; and
an interlayer dielectric (ILD) layer disposed over the first contact etch stop layer and the second contact etch stop layer, wherein:
a first topography variation between the first region of the wafer and the second region of the wafer is defined by a first difference in a first height of a first topmost surface of a first gate structure disposed in the first region of the wafer and a second height of a second topmost surface of a second gate structure disposed in the second region of the wafer,
the first contact etch stop layer has a first thickness and the second contact etch stop layer has a second thickness that is different than the first thickness,
a second topography variation between the first region of the wafer and the second region of the wafer is defined by a second difference in a third height of a third topmost surface of the first contact etch stop layer in the first region of the wafer and a fourth height of a fourth topmost surface of the second contact etch stop layer in the second region, and
the second topography variation is less than the first topography variation.

10. The integrated circuit device of claim 9 , wherein the first difference is greater than 10% and the second difference is less than or equal to about 10%.

11. The integrated circuit device of claim 9 , wherein the first contact etch stop layer includes a first silicon nitride material, the second contact etch stop layer includes a second silicon nitride material, and the ILD layer includes a low-k dielectric material.

12. The integrated circuit device of claim 9 , wherein the first thickness is about 600 Å to about 700 Å and the second thickness is about 700 Å to about 850 Å.

13. The integrated circuit device of claim 12 , wherein a third thickness of the ILD layer is about 5,000 Å to about 6,000 Å.

14. The integrated circuit device of claim 9 , wherein the first region of the wafer is directly adjacent to the second region of the wafer.

15. The integrated circuit device of claim 14 , wherein the first contact etch stop layer extends into the second region of the wafer, such that the second contact etch stop layer overlaps the first contact etch stop layer at an interface of the first region and the second region.

16. The integrated circuit device of claim 9 , wherein the first contact etch stop layer is further disposed in the second region of the wafer and the second contact etch stop layer is disposed between the ILD layer and the first contact etch stop layer.

17. An integrated circuit device comprising:
a first gate structure over a substrate in a first region;
a second gate structure over the substrate in a second region;
a first dielectric layer having a first thickness disposed over the first region, wherein the first dielectric layer is disposed over the first gate structure in the first region;
a second dielectric layer having a second thickness disposed over the second region, wherein the second dielectric layer is disposed over the second gate structure in the second region and the second thickness is greater than the first thickness;
a third dielectric layer disposed over the first dielectric layer in the first region and the second dielectric layer in the second region, wherein each of a first material of the first dielectric layer and a second material of the second dielectric layer is different than a third material of the third dielectric layer; and
an isolation feature disposed in the substrate at an interface of the first region and the second region, wherein the first dielectric layer is disposed over the isolation feature, the second dielectric layer is disposed over the isolation feature, the first dielectric layer is disposed over an entirety of a top surface of the isolation feature, and the second dielectric layer is disposed over a portion of the top surface of the isolation feature.

18. The integrated circuit device of claim 17 , wherein the first gate structure has a first height, the second gate structure has a second height, and the second height is less than the first height.

19. The integrated circuit device of claim 18 , wherein a difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

20. The integrated circuit device of claim 17 , wherein the second dielectric layer overlaps the first dielectric layer over the isolation feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Kuan-Wei
• Huang chun yu
• Lin Chih-Hsun
• Hsieh Ping-Pang

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title