Semiconductor device structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-2017117355-A1
Application number	US-201514924326-A
Country	US
Kind code	A1
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Apr 27, 2017
Grant date	—

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.

First claim

1 . A semiconductor device structure, comprising:
a substrate having a trench surrounding an active island of the substrate, wherein the active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall, the inclined surface is inclined relative to the top surface at a first angle, the sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle; an isolation structure in the trench, wherein a second inclined surface of the isolation structure and the inclined surface of the active island form sidewalls of a recess; a gate insulating layer over the top surface and the inclined surface; and a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the active island and extends into the recess, and the recess is filled with the gate.

2 . The semiconductor device structure as claimed in claim 1 , wherein the gate insulating layer has a first portion and a second portion, the first portion is over the inclined surface, the second portion is over the top surface, and a first thickness of the first portion is equal to or greater than a second thickness of the second portion.

3 . The semiconductor device structure as claimed in claim 2 , wherein the gate insulating layer is a continuous layer.

4 . The semiconductor device structure as claimed in claim 1 , wherein the gate insulating layer is in direct contact with the active island, the isolation structure, and the gate, and the gate insulating layer separates the gate from the active island.

5 . The semiconductor device structure as claimed in claim 1 , wherein the isolation structure does not cover the inclined surface.

6 . The semiconductor device structure as claimed in claim 1 , wherein the first angle ranges from about 110° to about 160°.

7 . The semiconductor device structure as claimed in claim 1 , wherein the gate insulating layer includes an oxide of a material of the active island.

8 . The semiconductor device structure as claimed in claim 1 , wherein the inclined surface comprises a (110) crystal orientation.

9 . A semiconductor device structure, comprising:
a substrate having a trench surrounding an active island of the substrate, wherein the active island has a top surface, a sidewall, and an inclined surface between the top surface and the sidewall, the inclined surface is inclined relative to the top surface at a first angle, the sidewall is inclined relative to the top surface at a second angle, the first angle is greater than the second angle, and the top surface, the sidewall, and the inclined surface are planar surfaces; an isolation structure in the trench, wherein a second inclined surface of the isolation structure and the inclined surface of the active island surround a recess; a gate insulating layer over the top surface and the inclined surface; and a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the active island and extends into the recess such that a bottom surface of the gate is within the recess, and the recess is filled with the gate.

10 . The semiconductor device structure as claimed in claim 9 , wherein the trench adjacent to the inclined surface has a first depth, the trench adjacent to the sidewall has a second depth, and the second depth is greater than the first depth.

11 . The semiconductor device structure as claimed in claim 9 , wherein the inclined surface has a first length, the sidewall has a second length, and the second length is greater than the first length.

12 . The semiconductor device structure as claimed in claim 9 , wherein the isolation structure covers the sidewall.

13 . The semiconductor device structure as claimed in claim 9 , wherein the isolation structure is not in direct contact with the inclined surface.

14 . The semiconductor device structure as claimed in claim 9 , wherein an interface between the top surface and the inclined surface forms a first ridge line, an interface between the inclined surface and the sidewall forms a second ridge line, and the first ridge line and the second ridge line does not intersect with each other.

15 . The semiconductor device structure as claimed in claim 9 , wherein the inclined surface comprises a (110) crystal orientation, and the top surface comprises a (100) crystal orientation.

16 - 20 . (canceled)

21 . A semiconductor device structure, comprising:
a substrate having a trench surrounding an active island of the substrate, wherein the active island has a first top surface, a first sidewall, and an first inclined surface connecting the first top surface to the first sidewall, the first inclined surface is inclined relative to the first top surface at a first angle, the first sidewall is inclined relative to the first top surface at a second angle, and the first angle is greater than the second angle; an isolation structure in the trench, wherein a recess is between the first inclined surface and a second inclined surface of the isolation structure; a gate insulating layer over the first top surface and the first inclined surface and extending into the recess; and a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the active island, and the gate extends into the recess such that a bottom surface of the gate is within the recess, and the recess is filled with the gate.

22 . The semiconductor device structure as claimed in claim 21 , wherein the isolation structure has a second top surface, and the second inclined surface is between and connected to the second top surface and the first sidewall.

23 . The semiconductor device structure as claimed in claim 21 , wherein the gate crosses the recess.

24 . The semiconductor device structure as claimed in claim 21 , wherein the recess surrounds the active island.

25 . The semiconductor device structure as claimed in claim 21 , wherein a first depth of the recess is less than a second depth of the trench.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• HSU Shih-Lu
• Hsieh Ping-Pang
• Lin Yu-Chu
• JHOU Jyun-Guan

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/244

  comprising alternated and repeated etching and passivation steps · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title