Floating gate isolation and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10818804-B2
Application number	US-201514925551-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one isolation structure;
forming a pair of tunneling oxide layers on a top surface of the at least one isolation structure;
forming a pair of floating gates on the tunneling oxide layers, respectively;
forming a pair of isolation layers covering tops of the floating gates and peripherally enclosing the floating gates, respectively, wherein the isolation layers are spaced apart from each other; and
forming a control gate over tops of the isolation layers and in direct contact with the isolation structure, wherein widths of the tunneling oxide layers and widths of the floating gates are substantially the same.

2. The method of claim 1 , wherein forming the tunneling oxide layers and forming the floating gates comprise:
forming an oxide layer covering the substrate;
forming a conductive layer on the oxide layer; and
removing a portion of the conductive layer and a portion of the oxide layer to respectively form the floating gates and the tunneling oxide layers.

3. The method of claim 1 , wherein forming the isolation layers comprises forming the isolation layers comprising a multi-layered structure.

4. The method of claim 1 , wherein forming the isolation layers comprises forming the isolation layers comprising an oxide-nitride-oxide (ONO) structure.

5. The method of claim 1 , wherein providing the substrate comprises providing the substrate having a plurality of active regions defined by the at least one isolation structure.

6. The method of claim 5 , wherein
forming the tunneling oxide layers is performed to form the tunneling oxide layers respectively on the active regions and a first portion of the at least one isolation structure;
forming the isolation layers is performed to form the isolation layers respectively covering the floating gates and peripherally enclosing the tunneling oxide layers and the floating gates; and
forming the control gate is performed to form the control gate extending on the isolation layers and a second portion of the at least one isolation structure between the tunneling oxide layers.

7. The method of claim 5 , wherein the at least one isolation structure comprises a shallow trench isolation structure.

8. A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one isolation structure;
forming an oxide layer blanketly covering the substrate;
forming a conductive layer blanketly covering the oxide layer;
removing a portion of the oxide layer and a portion of the conductive layer to respectively form at least one tunneling oxide layer on the substrate and at least one floating gate on the at least one tunneling oxide layer and on a top surface of the at least one isolation structure, wherein a width of the at least one floating gate is the same as a width of the at least one tunneling oxide layer;
forming at least one isolation layer covering a top of the at least one floating gate and peripherally enclosing the at least one tunneling oxide layer; and
forming a control gate over a top of the at least one isolation layer and in contact with the isolation structure, wherein forming the control gate is performed after removing the portion of the oxide layer and the portion of the conductive layer.

9. The method of claim 8 , wherein forming the at least one floating gate comprises forming the at least one floating gate from polysilicon.

10. The method of claim 8 , wherein forming the at least one isolation layer comprises forming the at least one isolation layer comprising an oxide-nitride-oxide structure.

11. The method of claim 8 , wherein forming the control gate comprises forming the control gate from polysilicon.

12. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided to have at least two active regions defined by at least one isolation structure disposed in the substrate;
forming at least two gate structures respectively on the active regions, wherein forming each of the gate structures comprises:
forming a tunneling oxide layer on the active region, wherein the tunneling oxide layer has a width greater than a width of a top surface of the active region;
control gate is in direct contact with the isolation layer forming a floating gate on the tunneling oxide layer; and
forming an isolation layer covering a top of the floating gate and peripherally enclosing the tunneling oxide layer and the floating gate; and

forming a control gate extending on the isolation layers and in direct contact with the at least one isolation structure between the gate structures, wherein no re-oxidation operation is performed on the gate structures to form an oxide layer on the gate structures.

13. The method of claim 12 , wherein forming the tunneling oxide layer and the floating gate comprise:
forming an oxide layer blanketly covering the substrate;
forming a conductive layer blanketly covering the oxide layer; and
removing a portion of the conductive layer and a portion of the oxide layer to respectively form the floating gate and the tunneling oxide layer.

14. The method of claim 12 , wherein forming the isolation layer comprises forming the isolation layer comprising a multi-layered structure.

15. The method of claim 12 , wherein forming the isolation layer comprises forming the isolation layer comprising an oxide-nitride-oxide structure.

16. The method of claim 12 , wherein the at least one isolation structure comprises a shallow trench isolation structure.

17. The method of claim 12 , wherein forming the control gate comprises:
forming a conductive layer blanketly covering the isolation layers, the at least one isolation structure, and the substrate; and
patterning the conductive layer to remove a portion of the conductive layer.

18. The method of claim 12 , wherein forming the isolation layer is such that the isolation layer is in contact with sidewalls of the tunneling oxide layer and the floating gate.

19. The method of claim 1 , wherein tunneling oxide layers are in contact with the top surface of the at least one isolation structure.

20. The method of claim 1 , wherein the floating gates are spaced apart from the top surface of the at least one isolation structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• HSU Shih-Lu
• Hsieh Ping-Pang
• LU Szu-Hsien
• Lin Yu-Chu

Classifications

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6891 Primary

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D1/00

  Resistors, capacitors or inductors · CPC title

• H10D30/683 Primary

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title