Methods for improving interlayer dielectric layer topography

Patent metadata

Field	Value
Publication number	US-10699960-B2
Application number	US-201816117241-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Jun 27, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.

First claim

What is claimed is:

1. A method comprising:
forming a first contact etch stop layer over a first region of a wafer, wherein a first topography variation exists between the first region and a second region of the wafer and the first contact etch stop layer has a first thickness;
forming a second contact etch stop layer over the second region of the wafer, wherein the second contact etch stop layer has a second thickness that is different than the first thickness to reduce the first topography variation to a second topography variation between the first region and the second region; and
forming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.

2. The method of claim 1 , wherein the second topography variation is a difference in a height of a topmost surface of the first contact etch stop layer in the first region and a height of a topmost surface of the second contact etch stop layer in the second region, wherein the difference is less than or equal to about 10%.

3. The method of claim 1 , wherein:
the forming the first contact etch stop layer includes:
depositing the first contact etch stop layer over the first region and the second region, and
etching the first contact etch stop layer from over the second region; and

the forming the second contact etch stop layer includes:
depositing the second contact etch stop layer over the first region and the second region, and
etching the second contact etch stop layer from over the first region.

4. The method of claim 3 , wherein:
the forming the first contact etch stop layer further includes:
performing a first lithography process to form a first mask layer over the first contact etch stop layer over the first region, and
removing the first mask layer after etching the first contact etch stop layer from over the second region; and

the forming the second contact etch stop layer further includes:
performing a second lithography process to form a second mask layer over the second contact etch stop layer over the second region, and
removing the second mask layer after etching the second contact etch stop layer from over the first region.

5. The method of claim 1 , wherein a first gate structure having a first height is disposed over the wafer in the first region and a second gate structure having a second height is disposed over the wafer in the second region, wherein the first topography variation is caused by the first height being different than the second height.

6. The method of claim 5 , wherein the second topography variation is caused by any difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness.

7. The method of claim 1 , wherein the first contact etch stop layer and the second contact etch stop layer include different material.

8. The method of claim 1 , wherein the first contact etch stop layer and the second contact etch stop layer include the same material.

9. The method of claim 1 , further comprising forming an intermetal dielectric layer over the ILD layer.

10. A method comprising:
forming a first contact etch stop layer over a first gate structure having a first height, wherein the first contact etch stop layer has a first thickness;
forming a second contact etch stop layer over a second gate structure having a second height that is less than the first height, wherein the second contact etch stop layer has a second thickness that is greater than the first thickness; and
forming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.

11. The method of claim 10 , wherein a difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%.

12. The method of claim 10 , wherein the first contact etch stop layer is formed before the second contact etch stop layer.

13. The method of claim 10 , wherein the first contact etch stop layer is formed after the second contact etch stop layer.

14. The method of claim 10 , wherein the forming the first contact etch stop layer over the first gate structure and the forming the second contact etch stop layer over the second gate structure includes:
depositing a first material layer having the first thickness over the first gate structure and the second gate structure;
etching the first material layer over the second gate structure;
depositing a second material layer having the second thickness over the second gate structure and the first material layer over the first gate structure; and
etching the second material layer over the first material layer.

15. The method of claim 14 , further comprising:
performing a first lithography process to form a first mask layer that covers the first material layer over the first gate structure during the etching of the first material layer; and
performing a second lithography process to form a second mask layer that covers the second material layer over the second gate structure during the etching of the second material layer.

16. The method of claim 15 , wherein the forming the first mask layer and the forming the second mask layer each include forming a patterned resist layer.

17. The method of claim 10 , wherein the forming the first contact etch stop layer over the first gate structure and the forming the second contact etch stop layer over the second gate structure includes:
depositing a first material layer over the first gate structure and the second gate structure;
depositing a second material layer over the first material layer; and
removing the second material layer from over the first gate structure, such that the first material layer forms the first contact etch stop layer having the first thickness over the first gate structure and the first material layer and the second material layer form the second contact etch stop layer over the second gate structure.

18. The method of claim 10 , wherein the forming the ILD layer includes:
depositing a low-k dielectric material over the first contact etch stop layer and the second contact etch stop layer; and
performing a planarization process on the low-k dielectric material, thereby planarizing a top surface of the low-k dielectric material.

19. A method comprising:
depositing a first dielectric layer having a first thickness over a first gate structure in a first region and a second gate structure in a second region;
forming a first mask layer that covers the first dielectric layer in the first region and exposes the first dielectric layer in the second region;
removing the exposed first dielectric layer in the second region;
removing the first mask layer;
depositing a second dielectric layer having a second thickness over the first dielectric layer in the first region and the second gate structure in the second region, wherein the second thickness is greater than the first thickness;
forming a second mask layer that covers the second dielectric layer in the second region and exposes the second dielectric layer in the first region, wherein the second mask layer covers a portion of the second dielectric layer disposed over the first dielectric layer proximate a boundary between the first region and the second region;
removing the exposed second dielectric layer in the first region;
removing the second mask layer; and
forming a third dielectric layer over the first dielectric layer in the first reg

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Kuan-Wei
• Huang chun yu
• Lin Chih-Hsun
• Hsieh Ping-Pang

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title