Apparatus and method for memory device

Patent metadata

Field	Value
Publication number	US-10164073-B2
Application number	US-201514685192-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Jul 12, 2012
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A method comprises forming a gate stack over a substrate, applying an oxygen flush process to the gate stack, forming a uniform oxide layer on the gate stack as a result of performing the step of applying the oxygen flush process and removing the uniform oxide layer through a pre-clean process.

First claim

What is claimed is:

1. A method comprising:
forming a gate stack over a substrate, wherein the gate stack comprises:
a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate; and
a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure;

applying an oxygen plasma process to the gate stack and the substrate to form an oxide layer on the substrate, on sidewalls of the first dielectric layer, on sidewalls of the first gate structure, on sidewalls of the second dielectric layer, on sidewalls of the second gate structure, and on a top surface of the second gate structure, wherein the oxygen plasma process is applied until a thickness of the oxide layer is from 20 Angstroms to 300 Angstroms;
after forming the oxide layer on the substrate, implanting ions in the substrate through the oxide layer to form a drain region and a source region;
removing all of the oxide layer from the substrate, the sidewalls of the first dielectric layer, the sidewalls of the first gate structure, the sidewalls of the second dielectric layer, the sidewalls of the second gate structure, and the top surface of the gate stack through a pre-clean process, a first recess and a second recess remaining in the substrate after removing all of the oxide layer, wherein the first recess and the second recess are on opposite sides of the gate stack; and
after the removing all of the oxide layer from the substrate, the sidewalls of the first dielectric layer, the sidewalls of the first gate structure, the sidewalls of the second dielectric layer, the sidewalls of the second gate structure, and the top surface of the gate stack, forming a gate oxide layer on the substrate, the sidewalls of the first dielectric layer, the sidewalls of the first gate structure, the sidewalls of the second dielectric layer, the sidewalls of the second gate structure, and the top surface of the gate stack.

2. The method of claim 1 , wherein:
the drain region is formed on an opposite side of the gate stack from the source region.

3. The method of claim 1 , wherein:
the oxygen plasma process is an oxygen plasma flush process performed in a dry etch chamber.

4. The method of claim 1 , wherein:
the first recess exposes a top surface of the drain region, the first recess extending vertically from the top surface of the drain region to a bottom surface of the first dielectric layer; and
the second recess exposes a top surface of the source region, the second recess extending vertically from the top surface of the source region to the bottom surface of the first dielectric layer.

5. The method of claim 1 , wherein:
the first recess extends laterally from the gate stack along the drain region; and
the second recess extends laterally from the gate stack along the source region.

6. The method of claim 1 , wherein the second dielectric layer is a SiO 2 —Si 3 N 4 —SiO 2 layer, and wherein the SiO 2 —Si 3 N 4 —SiO 2 layer is free of lateral undercuts after the forming the gate oxide layer.

7. A method comprising:
forming a gate stack structure over a substrate, wherein the gate stack structure comprises:
a tunneling layer formed over the substrate;
a floating gate formed over the tunneling layer;
a blocking layer formed over the floating gate; and
a control gate formed over the blocking layer;

applying an oxygen plasma process to the gate stack structure and the substrate to form an oxide layer on a top surface of the substrate, on sidewalls of the tunneling layer, on sidewalls of the floating gate, on sidewalls of the blocking layer, on sidewalls of the control gate, and on a top surface of the control gate, wherein the oxygen plasma process is applied in a dry etch chamber until a thickness of the oxide layer is from 20 Angstroms to 300 Angstroms;
after forming the oxide layer, implanting ions in the substrate through the oxide layer to form active regions on opposite sides of the gate stack structure;
removing all of the oxide layer from the top surface of the substrate, the sidewalls of the tunneling layer, the sidewalls of the floating gate, the sidewalls of the blocking layer, the sidewalls of the control gate, and the top surface of the control gate, recesses remaining in the substrate exposing surfaces of the active regions after removing all of the oxide layer; and
after removing all of the oxide layer, forming a gate oxide layer on the sidewalls of the tunneling layer, the sidewalls of the floating gate, the sidewalls of the blocking layer, the sidewalls of the control gate, the top surface of the control gate, and the exposed surfaces of the active regions.

8. The method of claim 7 , further comprising:
removing all of the oxide layer through a pre-clean process.

9. The method of claim 8 , wherein:
the pre-clean process is a wet cleaning process.

10. The method of claim 8 , further comprising:
after the step of removing all of the oxide layer from the substrate through the pre-clean process, forming the gate oxide layer physically contacting the sidewalls of the tunneling layer, the sidewalls of the floating gate, the sidewalls of the blocking layer, the sidewalls of the control gate, the top surface of the control gate, and the exposed surfaces of the active regions.

11. The method of claim 10 , wherein:
the gate oxide layer has a thickness in a range from 15 Angstroms to 300 Angstroms.

12. The method of claim 7 , wherein:
the recesses extend vertically from the exposed surfaces of the active regions to a bottom surface of the tunneling layer a distance of from 5 Angstroms to 200 Angstroms.

13. The method of claim 7 , wherein:
the recesses extend laterally from the gate stack structure along the active regions.

14. The method of claim 7 , wherein the blocking layer is an SiO 2 —Si 3 N 4 —SiO 2 layer free of lateral undercuts.

15. A method comprising:
forming a gate stack on a substrate;
applying an oxygen plasma process to the gate stack and the substrate to form a first oxide layer on the substrate and the gate stack, the first oxide layer having a thickness of from 20 Angstroms to 300 Angstroms along a top surface of the substrate, sides of the gate stack, and a top surface of the gate stack;
after forming the first oxide layer, applying an ion implantation process to the gate stack and the substrate, wherein through the ion implantation process, a drain region and a source region are formed under the first oxide layer on opposite sides of the gate stack;
applying a pre-cleaning process to the gate stack and the substrate, wherein all of the first oxide layer is removed from the top surface of the substrate, the sides of the gate stack, and the top surface of the gate stack after the pre-cleaning process, wherein after the step of applying the pre-cleaning process to the gate stack and the substrate:
a first recess is formed in the substrate, the first recess extending vertically from a top surface of the drain region to a bottom surface of the gate stack; and
a second recess is formed in the substrate, the second recess extending vertically from a top surface of the source region to the bottom surface of the gate stack; and

after all of the first oxide layer is removed from the top surface of the substrate, the sides of the gate stack, and the top surface of the gate stack, growing a second oxide layer on and physically contacting the sides and the top surface of the gate stack, in the first recess, and in the second recess.

16. The me

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Ping-Pang
• Lee Chih-Ming
• Chen Yu-Jen
• Jangjian Shiu-Ko

Classifications

• H01L29/66575

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/66825 Primary

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic