Gate structure with multiple spacer and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017032971-A1
Application number	US-201514815386-A
Country	US
Kind code	A1
Filing date	Jul 31, 2015
Priority date	Jul 31, 2015
Publication date	Feb 2, 2017
Grant date	—

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

First claim

1 - 12 . (canceled)

13 . A method for forming a semiconductor structure, comprising:
forming a floating gate structure over a substrate; forming a dielectric structure over the floating gate structure; forming a control gate structure over the dielectric structure; forming a word line structure at a first side of the floating gate structure; forming an erase gate structure at a second side of floating gate structure; forming a trench in the erase gate structure adjacent to the second side of floating gate structure; forming a lower spacer at a lower portion of a sidewall of the trench; and forming an upper spacer over the lower spacer at an upper portion of the sidewall of the trench.

14 . The method for forming a semiconductor structure as claimed in claim 13 , further comprising:
forming a common source region adjacent to the floating gate structure before the erase gate structure is formed, such that the erase gate structure is formed over the common source region.

15 . The method for forming a semiconductor structure as claimed in claim 14 , further comprising:
filling the trench with an interlayer dielectric layer; and forming a contact through the interlayer dielectric layer over the common source region.

16 . The method for forming a semiconductor structure as claimed in claim 13 , wherein the trench in the erase gate structure is formed by performing an etching process.

17 . The method for forming a semiconductor structure as claimed in claim 16 , wherein a portion of the control gate structure is removed during the etching process.

18 . The method for forming a semiconductor structure as claimed in claim 16 , wherein a portion of the floating gate structure is removed during the etching process.

19 . The method for forming a semiconductor structure as claimed in claim 13 , wherein the upper spacer is in direct contact with the control gate structure.

20 . The method for forming a semiconductor structure as claimed in claim 13 , wherein the lower spacer is in direct contact with the floating gate structure.

21 . A method for forming a semiconductor structure, comprising:
forming a floating gate structure over a substrate; forming a dielectric structure over the floating gate structure; forming a control gate structure over the dielectric structure; forming an erase gate structure adjacent to a side of floating gate structure; removing a portion of the erase gate structure to form a trench; and forming a spacer on a sidewall of the trench, wherein a portion of the control gate structure is removed when forming the trench.

22 . The method for forming a semiconductor structure as claimed in claim 21 , further comprising:
forming an interlayer dielectric layer in the trench; and forming a contact though the interlayer dielectric layer.

23 . (canceled)

24 . The method for forming a semiconductor structure as claimed in claim 21 , further comprising:
forming a word line structure adjacent to another side of the floating gate structure opposite to the erase gate structure.

25 . The method for forming a semiconductor structure as claimed in claim 21 , wherein a portion of the spacer is in direct contact with the control gate structure.

26 . A method for forming a semiconductor structure, comprising:
forming a floating gate structure over a substrate; forming a dielectric layer over the floating gate structure; forming a control gate structure over the dielectric layer; forming a first spacer over a sidewall of the control gate structure; forming an erase gate structure adjacent to the first spacer over the substrate; removing a portion of the erase gate structure to form a trench by performing an etching process; and forming an additional spacer on a sidewall of the trench, wherein a portion of the additional spacer is formed on the first spacer.

27 . The method for forming a semiconductor structure as claimed in claim 26 , further comprising:
forming an interlayer dielectric layer in the trench; and forming a contact though the interlayer dielectric layer.

28 . The method for forming a semiconductor structure as claimed in claim 26 , wherein a portion of the first spacer is removed during the etching process.

29 . The method for forming a semiconductor structure as claimed in claim 26 , wherein a portion of the control gate structure is removed during the etching process.

30 . The method for forming a semiconductor structure as claimed in claim 26 , wherein a portion of the floating gate structure is removed during the etching process.

31 . (canceled)

32 . The method for forming a semiconductor structure as claimed in claim 28 , wherein the additional spacer is formed on the first spacer and extends onto a sidewall of the control gate structure.

33 . The method for forming a semiconductor structure as claimed in claim 26 , wherein a portion of the control gate structure is exposed by the trench.

34 . The method for forming a semiconductor structure as claimed in claim 13 , further comprising:
forming a first spacer over a sidewall of the control gate structure before the erase gate structure is formed; and a portion of the first spacer is removed when the trench is formed in the erase gate structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Chia-Ming
• Chuang Chiang-Ming
• Ho Pei-Chi
• Hsieh Ping-Pang

Classifications

• H01L27/11521

  Electricity · mapped topic

• H01L21/28273 Primary

  Electricity · mapped topic

• H01L29/788

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic