Formation of semiconductor device with resistors

Patent metadata

Field	Value
Publication number	US-2016233215-A1
Application number	US-201615134272-A
Country	US
Kind code	A1
Filing date	Apr 20, 2016
Priority date	Nov 27, 2013
Publication date	Aug 11, 2016
Grant date	—

Abstract

A semiconductor device includes a semiconductor substrate, trench isolations, a sacrificial layer, a first resist protect oxide (RPO) layer, a second RPO layer and a silicide layer. The semiconductor substrate has first portions and second portions which are alternately disposed, and each of the second portions includes a first resist region with a first resistance, a second resist region with a second resistance and a silicide region. The second resistance is greater than the first resistance. The trench isolations are in the first portions. The sacrificial layer is on the first resist region. The first RPO layer is on the sacrificial layer. The first RPO layer together with the sacrificial layer have a first thickness. The second RPO layer is on the second resist region, in which the second RPO layer has a second thickness smaller than the first thickness. The silicide layer is on the silicide region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate with a plurality of first portions, a first resist region with a first resistance, a second resist region with a second resistance, and a silicide region, wherein the first resist region is disposed between two adjacent first portions, and the second resist region is disposed between first another two adjacent first portions, and the silicide region is disposed between second another two adjacent first portions, and the second resistance is greater than the first resistance; a plurality of trench isolations in the first portions of the semiconductor substrate; a sacrificial layer on the first resist region; a first resist protect oxide layer on the sacrificial layer, wherein the first resist protect oxide layer together with the sacrificial layer have a first thickness; a second resist protect oxide layer on the second resist region, wherein the second resist protect oxide layer has a second thickness smaller than the first thickness; and a silicide layer on the silicide region.

2 . The device of claim 1 , wherein a doping concentration of the first resist region is substantially in a range from 10 14 to 10 16 /cm 3 .

3 . The device of claim 2 , wherein a doping concentration of the second resist region is substantially in a range from 10 11 /cm 3 to 10 14 /cm 3 .

4 . The device of claim 1 , wherein the first thickness is substantially in a range from 10 to 110 nm and the second thickness is substantially greater than 0 and smaller than or equal to 30 nm.

5 . The device of claim 1 , wherein the first resist protect oxide layer has a third thickness the same with the second thickness.

6 . The device of claim 1 , wherein the first resist region and the second resist region and the silicide region comprise boron-doped, phosphor-doped, arsenic-doped or carbon-doped portions.

7 . The device of claim 1 , wherein the silicide region comprises boron-doped, phosphor-doped, arsenic-doped or carbon-doped portions.

8 . The device of claim 1 , wherein the first resistance is substantially in a range from 100 Ohm/sqr to 400 Ohm/sqr.

9 . The device of claim 1 , wherein the second resistance is substantially in a range from 300 Ohm/sqr to 3000 Ohm/sqr.

10 . The device of claim 1 , wherein the first resist protect oxide layer comprises silicon oxide, silicon oxynitride (SiON), silicon nitride, or a composite thereof.

11 . The device of claim 1 , wherein the second resist protect oxide layer comprises silicon oxide, silicon oxynitride (SiON), silicon nitride, or a composite thereof.

12 . The device of claim 1 , wherein the sacrificial layer is a screen oxide.

13 . A semiconductor device, comprising:
a semiconductor substrate with a plurality of first portions, a first resist region with a first resistance, and a second resist region with a second resistance, wherein the first resist region is disposed between two adjacent first portions, and the second resist region is disposed between another two adjacent first portions, and the second resistance is greater than the first resistance; a plurality of trench isolations in the first portions of the semiconductor substrate; and a sacrificial layer on the first resist region.

14 . The device of claim 13 , wherein a doping concentration of the first resist region is substantially in a range from 10 14 to 10 16 /cm 3 .

15 . The device of claim 14 , wherein a doping concentration of the second resist region is substantially in a range from 10 11 /cm 3 to 10 14 /cm 3 .

16 . The device of claim 13 , wherein the first resist region comprises boron-doped, phosphor-doped, arsenic-doped or carbon-doped portions.

17 . The device of claim 13 , wherein the second resist region comprises boron-doped, phosphor-doped, arsenic-doped or carbon-doped portions.

18 . The device of claim 13 , wherein the first resistance is substantially in a range from 100 Ohm/sqr to 400 Ohm/sqr.

19 . The device of claim 13 , wherein the second resistance is substantially in a range from 300 Ohm/sqr to 3000 Ohm/sqr.

20 . The device of claim 13 , wherein the sacrificial layer is a screen oxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yu-Jen
• Hsieh Ping-Pang
• Chen Hsin-Chi

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title