Floating gate isolation

Patent metadata

Field	Value
Publication number	US-11581441-B2
Application number	US-202017079103-A
Country	US
Kind code	B2
Filing date	Oct 23, 2020
Priority date	Oct 28, 2015
Publication date	Feb 14, 2023
Grant date	Feb 14, 2023

Abstract

A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a tunneling oxide layer over the substrate;
a floating gate over the tunneling oxide layer, wherein a width of the tunneling oxide layer and a width of the floating gate are substantially the same;
an isolation layer covering a top of the floating gate and peripherally enclosing the tunneling oxide layer and the floating gate; and
a control gate over a top of the isolation layer, wherein a bottom surface of the control gate is substantially coplanar with a bottom surface of the isolation layer.

2. The semiconductor device of claim 1 , wherein the floating gate comprises a polysilicon layer.

3. The semiconductor device of claim 1 , wherein the isolation layer comprises a multi-layered structure.

4. The semiconductor device of claim 1 , wherein the isolation layer comprises a first oxide layer, a nitride layer and a second oxide layer stacked in sequence.

5. The semiconductor device of claim 1 , wherein the control gate comprises a polysilicon layer.

6. The semiconductor device of claim 1 , wherein the bottom surface of the control gate is lower than a top surface of the floating gate.

7. The semiconductor device of claim 1 , wherein the bottom surface of the control gate is lower than a top surface of the tunneling oxide layer.

8. A semiconductor device, comprising:
a substrate having at least two active regions defined by at least one isolation structure in the substrate;
at least two gate structures respectively over the active regions, wherein each of the gate structures comprises:
a tunneling oxide layer over one of the active regions and a first portion of the at least one isolation structure;
a floating gate over the tunneling oxide layer; and
an isolation layer covering a top of the floating gate and peripherally enclosing the tunneling oxide layer and the floating gate; and

a control gate extending on the isolation layer and a second portion of the at least one isolation structure between the gate structures, wherein the control gate is in contact with the at least one isolation structure.

9. The semiconductor device of claim 8 , wherein the at least one isolation structure comprises a shallow trench isolation structure.

10. The semiconductor device of claim 8 , wherein the floating gate of each of the gate structures comprises a polysilicon layer.

11. The semiconductor device of claim 8 , wherein the isolation layer of each of the gate structures comprises a multi-layered structure.

12. The semiconductor device of claim 9 , wherein the isolation layer of each of the gate structures comprises a first oxide layer, a nitride layer and a second oxide layer stacked in sequence.

13. The semiconductor device of claim 8 , wherein the control gate comprises a polysilicon layer.

14. The semiconductor device of claim 8 , wherein the isolation layer of each of the gate structures is in contact with the at least one isolation structure.

15. A semiconductor device, comprising:
a substrate having a first active region and a second active region;
a first isolation structure and a second isolation structure in the substrate, wherein the first active region is between the first and second isolation structures, and the second isolation structure is between the first active region and the second active region;
a first floating gate over the first active region;
a second floating gate over the second active region;
a first tunneling oxide layer between the first active region and the first floating gate, wherein the first tunneling oxide layer is in contact with both the first and second isolation structures and a width of the first tunneling oxide layer and a width of the first floating gate are substantially the same;
a second tunneling oxide layer between the second active region and the second floating gate and a width of the second tunneling oxide layer and a width of the second floating gate are substantially the same;
a first isolation layer covering the first floating gate and peripherally enclosing the first tunneling oxide layer and the first floating gate;
a second isolation layer covering the second floating gate and peripherally enclosing the second tunneling oxide layer and the second floating gate and spaced apart from the first isolation layer; and
a control gate above the first floating gate and the second floating gate, wherein a bottom surface of the control gate is substantially coplanar with a bottom surface of the first isolation layer.

16. The semiconductor device of claim 15 , wherein the first isolation layer is in contact with both the first and second isolation structures.

17. The semiconductor device of claim 15 , wherein the bottom surface of the control gate is lower than a bottom surface of the first floating gate.

18. The semiconductor device of claim 15 , wherein a first portion of the first floating gate is directly above the first isolation structure.

19. The semiconductor device of claim 18 , wherein a second portion of the first floating gate is directly above the second isolation structure.

20. The semiconductor device of claim 15 , wherein the bottom surface of the control gate is lower than a top surface of the first tunneling oxide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• HSU Shih-Lu
• Hsieh Ping-Pang
• LU Szu-Hsien
• Lin Yu-Chu

Classifications

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6891 Primary

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D1/00

  Resistors, capacitors or inductors · CPC title

• H10D30/683 Primary

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title