Memory failure prediction and mitigation
US-2026079801-A1 · Mar 19, 2026 · US
This page is not indexed by search engines while we improve data quality.
Majumdar Amitava patents
Majumdar Amitava is listed as an inventor on 103 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Majumdar Amitava |
| Total patents | 103 |
| First publication | Sep 27, 2016 |
| Latest publication | Mar 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Address mapping for improved memory reliability
US-12555623-B2 · Feb 17, 2026 · US
Socket design for a memory device
US-12548621-B2 · Feb 10, 2026 · US
DFxNoC—a multi-protocol, multi-cast, and multi-root network-on-chip with dynamic resource allocation
US-12537521-B2 · Jan 27, 2026 · US
Transceiver loopback testing
US-2026025212-A1 · Jan 22, 2026 · US
Memory failure prediction and mitigation
US-12511205-B2 · Dec 30, 2025 · US
Finite time counting period counting of infinite data streams
US-2025378864-A1 · Dec 11, 2025 · US
System for predicting properties of structures, imager system, and related methods
US-12462370-B2 · Nov 4, 2025 · US
Transceiver loopback testing
US-12451977-B2 · Oct 21, 2025 · US
Deterministic built-in self-test
US-2025292853-A1 · Sep 18, 2025 · US
Recent patents
Latest publications not already listed above.
Error detection, correction, and media management on a dram device
US-12354692-B2 · Jul 8, 2025 · US
Error detection, correction, and media management on a memory device
US-12347512-B2 · Jul 1, 2025 · US
Transceiver loopback testing
US-2025211341-A1 · Jun 26, 2025 · US
Selective per die DRAM PPR for memory device
US-12340861-B2 · Jun 24, 2025 · US
Semiconductor device including test structure and method
US-2025167055-A1 · May 22, 2025 · US
Row hammer telemetry
US-2025053343-A1 · Feb 13, 2025 · US
Finite time counting period counting of infinite data streams
US-12217824-B2 · Feb 4, 2025 · US
Area-optimized row hammer mitigation
US-12182413-B2 · Dec 31, 2024 · US
Memory device security and row hammer mitigation
US-2024411466-A1 · Dec 12, 2024 · US
Memory failure prediction and mitigation
US-2024403177-A1 · Dec 5, 2024 · US
Row hammer telemetry
US-12131071-B2 · Oct 29, 2024 · US
DFxNoC - A MULTI-PROTOCOL, MULTI-CAST, AND MULTI-ROOT NETWORK-ON-CHIP WITH DYNAMIC RESOURCE ALLOCATION
US-2024356544-A1 · Oct 24, 2024 · US
Electron beam probing techniques and related structures
US-2024355685-A1 · Oct 24, 2024 · US
Socket design for a memory device
US-2024347107-A1 · Oct 17, 2024 · US
Practical and efficient row hammer error detection
US-12119043-B2 · Oct 15, 2024 · US
Intra-chip and inter-chip data protection
US-12105658-B2 · Oct 1, 2024 · US
Memory device security and row hammer mitigation
US-12067270-B2 · Aug 20, 2024 · US
Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive
US-12032443-B2 · Jul 9, 2024 · US
Instant write scheme with delayed parity/raid
US-12019516-B2 · Jun 25, 2024 · US
Method and memory system for writing data to dram submodules based on the data traffic demand
US-12013756-B2 · Jun 18, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 71 |
| Xilinx Inc | 32 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C13/0004 | 24 |
| H10P74/207 | 23 |
| G11C13/0069 | 20 |
| G11C13/0026 | 18 |
| G11C13/0028 | 18 |