DFxNoC - A MULTI-PROTOCOL, MULTI-CAST, AND MULTI-ROOT NETWORK-ON-CHIP WITH DYNAMIC RESOURCE ALLOCATION

Patent metadata

Field	Value
Publication number	US-2024356544-A1
Application number	US-202318138008-A
Country	US
Kind code	A1
Filing date	Apr 21, 2023
Priority date	Apr 21, 2023
Publication date	Oct 24, 2024
Grant date	—

Abstract

Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.

First claim

What is claimed is:

1 . An integrated circuit (IC) device, comprising:
a plurality of end-points (EPs) that comprise functional circuitry; a first root device; and a bus network comprising multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the first root device, and the EPs; wherein the first root device is configured to output a first clock to the bus network; and wherein the multi-port switch circuits are dynamically configurable to route the first clock from the first root device to a first selectable set of one or more of the EPs over the network of fixed links.

2 . The IC device of claim 1 , wherein:
the multi-port switch circuits are further dynamically configurable to route data from the first root device to the selectable set of one or more of the EP over a first set of the fixed links, and to route response data from the selectable set of one or more of the EPs to the first root device over a second set of the fixed links.

3 . The IC device of claim 2 , wherein a first one of the multi-port switch circuits comprises a first port configured to receive the data and the first clock from the first root device, and a second port that comprises:
synchronous output circuitry configured to output the data received at the first port, synchronous with the first clock; bypass output circuitry configured to output the data received at the first port, asynchronously; and control circuitry that is dynamically configurable to provide the output of a selectable one of the synchronous output circuitry and the bypass output circuitry to a data output of the second port.

4 . The IC device of claim 2 , further comprising interface circuitry configured to interface between a first one of the multi-port switch circuits and a first one of the EPs, wherein the first multi-port switch circuit comprises first and second ports, and wherein:
the first port comprises an N-bit data input configured to receive the data from the first root device, and a clock input configured to receive the first clock from the first root device, wherein N is a positive integer; the second port is configured to provide the data received from the first root device to the interface circuitry over an N-bit data link, synchronous with the first clock, and to provide the first clock to the interface circuitry; the interface circuitry comprises first frequency converter circuitry configured to alter a data rate of data received over the N-bit data link by a factor of K to provide K×n bits of data at the reduced data rate, wherein K and n are positive integers; and the interface circuitry further comprises input permutation circuitry that is dynamically configurable to assign a selectable subset of n-bits of the K×n bits of data to the first EP over an n-bit data link at the reduced data rate.

5 . The IC device of claim 4 , wherein the interface circuitry further comprises:
input delay circuitry that is configurable to delay the n-bits of data by a selectable number of cycles of the first clock.

6 . The IC device of claim 4 , wherein interface circuitry further comprises:
output permutation circuitry comprising an m-bit input configured to receive m-bit response data from the first EP, a K×m-bit output, wherein the output permutation circuitry is dynamically configurable to assign the m-bit response data to a selectable subset of the K×m-bit output; and second frequency conversion circuitry configured to alter a data rate of the K×m-bit output of the output of the output permutation circuitry by the factor K to convert the K×m-bit output of the permutation circuitry to M-bit response data having the increased data rate.

7 . The IC device of claim 6 , wherein:
the output permutation circuitry further comprises circuitry configured to set unselected bits of the K×m-bit output of the permutation circuitry to a predetermined state; the second port of the first multi-port switch circuit is configured to receive the M-bit response data from the interface circuit; and the first port of the first multi-port switch circuit further comprises circuitry configured to merge the M-bit response data with M-bit response data received at one or more other ports of the first multi-switch circuit.

8 . The IC device of claim 6 , wherein the interface circuitry further comprises:
output delay circuitry that is configurable to delay the m-bits response data by a selectable number of cycles of the first clock.

9 . The IC device of claim 2 , wherein:
the first root device is further configured to provide loopback data to the bus network; and the bus network further comprises loop-back circuitry that is dynamically configurable to route the loopback data back to the first root device.

10 . The IC device of claim 1 , further comprising a second root device configured to output a second clock to the bus network, wherein a first one of the multi-port switch circuits comprises:
a first port that comprises a first clock input configured to receive the first clock from the first root device; a second port that comprises a second clock input configured to receive the second clock from the second root device; and clock selection circuitry that is dynamically configurable to provide a selectable one of the first and second clocks to a clock output of the first multi-port switch circuit.

11 . The IC device of claim 1 , further comprising a second root device configured to output a second clock to the bus network, wherein the multi-port switch circuits are further dynamically configurable to route the second clock from the second root device to a second selectable set of one or more of the EPs.

12 . The IC device of claim 11 , wherein the multi-port switch circuits are further dynamically configurable to simultaneously route the first and second clocks to the respective first and second selectable set of one or more of the EPs.

13 . The IC device of claim 11 , wherein the multi-port switch circuits are further dynamically configurable to:
route data formatted in accordance with a first protocol from the first root device to the first selectable set of one or more of the EPs; and route data formatted in accordance with a second protocol from the second root device to the second selectable set of one or more of the EPs; wherein the first and second protocols differ from one another.

14 . The IC device of claim 2 , wherein the bus network is protocol-agnostic.

15 . The IC device of claim 2 , wherein the first root device is configurable to output data formatted in accordance with a selectable one of multiple protocols to the bus network.

16 . The IC device of claim 20 , wherein the first root device comprises:
multiple protocol engines, each comprising circuitry configured to format data based on a respective one of multiple protocols; stimulus derivation circuitry that is configurable to output the formatted data of a selectable one of the protocol engines to the bus network; and response derivation circuitry that is configurable to provide response data received from the bus network to a selectable one of the protocol engines.

17 . The IC device of claim 2 , wherein:
the bus network is further dynamically configurable to simultaneously route the data from the first root device to multiple ones of the EPs, and to route response data from the multiple EPs to the first root device.

18 . The IC device of claim 17 , further comprising:
delay circuitry that is configurable to delay the data to a first one of the mult

Assignees

• Xilinx Inc

Inventors

• Nerukonda Rambabu
• Lin Albert Shih-Huai
• Borra Sreedhar
• Chadha Rajat
• Majumdar Amitava

Classifications

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F15/17312

  Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion (routing on a LAN H04L45/00) · CPC title

• H04L12/40

  Bus networks · CPC title