Practical and efficient row hammer error detection

Patent metadata

Field	Value
Publication number	US-12119043-B2
Application number	US-202217898737-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	Jan 27, 2022
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

First claim

What is claimed is:

1. An apparatus, comprising:
at least one static random access memory (SRAM) comprising a plurality of counters, each counter comprising a row identifier and a count, and a total number of counters in the plurality of counters being less than a total number of rows monitored by a memory error detector in a memory media device; and
a circuitry configured to perform operations comprising:
identifying whether a row identifier of a memory media access request is in the plurality of counters;
when the row identifier of the memory media access request is identified in the plurality of counters, updating the count of the counter corresponding to the row identifier in the plurality of counters, and if the count exceeds a predetermined threshold,
triggering a response to an error in the memory media device; and
when the row identifier of the memory media access request is not identified in the plurality of counters, updating the counter of the plurality of counters to include the row identifier of the memory media access request.

2. The apparatus according to claim 1 , configured to monitor all rows of one bank of a plurality of banks of the memory media device.

3. The apparatus according to claim 1 , wherein the SRAM comprises a plurality of single port SRAM.

4. The apparatus according to claim 1 , wherein the plurality of counters comprises a first table comprising the row identifiers and a second table comprising the respective count associated with each row identifier in the first table.

5. The apparatus according to claim 4 , wherein the identifying whether the row identifier of the memory media access request is in the plurality of counters comprises searching the first table to determine whether a matching entry for the row identifier of the memory access request is present in the first table.

6. The apparatus according to claim 5 , wherein the searching is a serial search of the first table.

7. The apparatus according to claim 5 , wherein the updating of the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the second table and inserting the row identifier in the first table in a location that corresponds to the identified minimum count in the second table; and
incrementing the identified minimum count in the second table.

8. The apparatus according to claim 7 , wherein the identifying the minimum value in the second table is at least partially performed in parallel with said searching the first table.

9. The apparatus according to claim 7 , wherein the identifying the minimum value in the second table includes considering a sticky bit associated with each count value in the second table.

10. The apparatus according to claim 1 , wherein the operations provide deterministic detection of row hammer attacks on the memory media device.

11. The apparatus according to claim 1 , wherein the memory media device is dynamic random access memory (DRAM), and wherein the respective bank corresponds to a plurality of rows in the DRAM.

12. The apparatus according to claim 1 , wherein the circuit is further configured to clear the plurality of counters in each refresh interval of the memory media device.

13. The apparatus according to claim 1 , wherein the response comprises a digital refresh management (DRFM) command to refresh one or more physically adjacent rows of a row corresponding to the row identifier.

14. A method comprising:
identifying, by a circuit whether a row identifier of a memory media access request is in a plurality of counters stored in at least one static random access memory (SRAM), wherein each counter of the plurality of counters comprises a row identifier and a count, and a total number of counters in the plurality of counters is less than a total number of rows monitored by the circuit in a memory media device;
when the row identifier of the memory media access request is identified in the plurality of counters, updating the count of the counter corresponding to the row identifier in the plurality of counters, and if the updated count exceeds a predetermined threshold, triggering a response to an error in the memory media device; and
when the row identifier of the memory media access request is not identified in the plurality of counters, updating the counter of the plurality of counters to include the row identifier of the memory media access request.

15. The method according to claim 14 , wherein the plurality of counters comprises a first table comprising the row identifiers and a second table comprising the respective count associated with each row identifier in the first table, and wherein the determining whether the row identifier of the memory media access request is in the plurality of counters comprises searching the first table to determine whether a matching entry for the row identifier of the memory access request is present in the first table.

16. The method according to claim 15 , wherein the updating of the counter of the plurality of counters to include the row identifier comprises:
identifying a minimum count in the second table and inserting the row identifier in the first table in a location that corresponds to the identified minimum count in the second table; and
incrementing the identified minimum count in the second table.

17. A memory controller comprising:
a first interface to a host system;
a second interface coupled to a memory media device, wherein the second interface comprises a plurality of physical interfaces to the memory media device and each of the physical interfaces correspond to a respective channel having a plurality of banks;
a plurality of devices, each device comprising:
at least one static random access memory (SRAM) comprising a plurality of counters, each counter comprising a row identifier and a count, and a total number of counters in the plurality of counters being less than a total number of rows monitored by the device in the memory media device; and
a circuit configured to perform operations comprising:
identifying whether a row identifier of the memory media access request is in the plurality of counters;
when the row identifier of the memory media access request is identified in the plurality of counters, updating the count of the counter corresponding to the row identifier in the plurality of counters, and if the updated count exceeds a predetermined threshold, triggering a response to an error in the memory media device; and
when the row identifier of the memory media access request is not identified in the plurality of counters, updating the counter of the plurality of counters to include the row identifier of the memory media access request.

18. The memory controller according to claim 17 , wherein each said device is configured to monitor all rows of a respective bank of the plurality of banks.

19. The memory controller according to claim 17 , wherein the plurality of counters comprises a first table comprising the row identifiers and a second table comprising the respective count associated with each row identifier in the first table.

20. The memory error detector according to claim 1 , wherein the operations provide deterministic detection of row hammer attacks on the memory media device.

Assignees

• Micron Technology Inc

Inventors

• Gieske Edmund
• Ayyapureddi Sujeet
• Lu Yang
• Majumdar Amitava

Classifications

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title