Selective per die DRAM PPR for memory device

Patent metadata

Field	Value
Publication number	US-12340861-B2
Application number	US-202318169635-A
Country	US
Kind code	B2
Filing date	Feb 15, 2023
Priority date	Sep 21, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

First claim

What is claimed is:

1. A tangible, non-transitory, computer readable storage medium comprising instructions which, when executed by a processor of a computer system, causes the processor to execute a method comprising:
reading a data block from a first memory address of a dynamic random-access memory of the computer system;
identifying an error in the data block via the processor of the computer system, wherein identifying the error comprises identifying both a row of the first memory address and a die where the error occurred within the row;
correcting the error via the processor generating a corrected data;
writing the corrected data back to the first memory location;
reading the data back from the first memory address to obtain a read-back data;
identifying whether the read-back data has an error or not;
upon determining that the read-back data has an error:
identifying that the die where the error occurred within the first memory address is in need of repair;
upon identifying that the first memory address is in need of repair, repairing the die within the first memory address where the error occurred;
recording the address of the memory error in a long-term historical storage of memory errors; and
upon determining that the read-back data does not have an error, determining that the first memory address has a historical storage record of read errors or that the first memory address does not have a historical storage record of read errors.

2. The computer readable storage medium of claim 1 , wherein the method further comprises:
upon determining that the read-back data does not have an error, and that the first memory address does not have a history of read errors, recording the address of the memory error in the long-term historical error storage.

3. The computer readable storage medium of claim 1 , wherein the method further comprises:
upon determining that the read-back data does not have an error, and that the first memory address does have a history of read errors, identifying that the first memory address is in need of repair or that the first memory address is not in need of repair; and
recording the location of the memory error in the long-term historical error storage.

4. The computer readable storage medium of claim 3 , wherein the method further comprises identifying that the first memory address is in need of repair or that the first memory address is not in need of repair further comprises:
identifying from the long-term historical storage of memory errors at least one of: a number of historical memory errors for the first memory address and a time frequency of historical memory errors for the first memory address; and
determining that the first memory address is in need of repair based upon at last one of: the number of historical memory errors exceeding a designated error threshold and the time frequency of historical memory errors exceeding a designated time frequency threshold.

5. The computer readable storage medium of claim 4 , wherein the method further comprises:
upon determining that the first memory address is in need of repair, performing either a soft post package repair or a hard post package repair to the errored die of row in need of repair.

6. The computer readable storage medium of claim 1 , wherein the method further comprises repairing the memory address further comprises performing either a soft post package repair or a hard post package repair to the errored die of row in need of repair.

7. The computer readable storage medium of claim 1 , wherein the method further comprises identifying the die where the error occurred within the row comprises performing at least error analysis via chipkill logic and performing an error analysis via ECC logic.

8. A tangible, non-transitory, computer readable storage medium comprising instructions which, when executed by a processor of a computer system, causes the processor to execute a method comprising:
reading a data block from a first memory address of a dynamic random access memory of the computer system;
identifying via the processor of the computer system an error in the data block, wherein identifying the error comprises identifying both a row of the first memory address and a die where the error occurred within the row;
further identifying that the first memory address is in need of post package repair (PPR);
upon identifying that the first memory address is in need of PPR, wherein a repair comprises identifying a second memory address to replace the first memory address, establishing a priority among any errors and repairs to the errors;
upon prioritizing the repairs, determining if a matching respective soft PPR memory location or a respective hard PPR memory location is available, including identifying if a die in in the second memory address corresponding to where the error occurred in the row is available for PPR; and
upon determining that the respective soft or hard PPR memory location is available, storing a corrected data block in a corresponding die of the respective soft or hard PPR memory location.

9. The computer readable storage medium of claim 8 , wherein the method further comprises:
for a repair which has been prioritized as a soft PPR, and upon determining that a soft PPR memory location is not available, storing the corrected data block in the hard PPR memory location; and
for a repair which has been prioritized as a hard PPR, and upon determining that a hard PPR memory location is not available, storing the corrected data block in a soft PPR memory location.

10. The computer readable storage medium of claim 8 , wherein the method further comprises: maintaining a long-term historical storage of memory errors; and
wherein the prioritizing the repair as a soft PPR or as a hard PPR further comprises determining a probability that the memory location is prone to becoming an uncorrectable memory location, wherein a memory location determined based on its error history to have a higher probability of becoming an uncorrectable memory is designated for a higher priority for hard PPR.

11. The computer readable storage medium of claim 10 , wherein the method further comprises determining a probability that the memory location is prone to becoming an uncorrectable memory location comprises determining if the first memory address has more than a threshold number of memory errors based on its history of memory errors in the long-term historical error storage.

12. The computer readable storage medium of claim 8 , wherein the method further comprises determining a likelihood the memory location is likely to become an uncorrectable memory location further comprises determining if the first memory address has more than a threshold frequency of memory errors based on its history of memory errors in the long-term historical storage.

13. The computer readable storage medium of claim 8 , wherein the method further comprises determining a likelihood the memory location is likely to becoming an uncorrectable memory location further comprises determining a historical type of memory error for the first memory address.

14. A memory system, comprising:
a transaction layer configured to interface with a host processor;
a memory controller with a physical layer configured to interface with a dynamic random-access memory (DRAM);
an error logic block (ELB) configured to identify a data read error in a data block read from DRAM and provide error correction for the data read error from the DRAM data block, said identification comprising an identification of a specific die in a specific row where the data read error occurred;
a persistent

Assignees

• Micron Technology Inc

Inventors

• Majumdar Amitava
• Hendrix Greg S
• Nagendrakumar Anandhavel
• Patel Krunal
• Shenoy Kirthi
• Caraccio Danilo
• Lal Ankush
• Ross Frank F
• Gailey Adam D

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/4401

  for self repair · CPC title