Intra-chip and inter-chip data protection

Patent metadata

Field	Value
Publication number	US-12105658-B2
Application number	US-202117477185-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Sep 16, 2021
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.

First claim

What is claimed is:

1. An integrated circuit (IG), comprising:
a communication network;
data circuitry configured to send a write request over the communication network;
a memory controller configured to receive the write request from the communication network and write data of the write request to a memory device;
first processing circuitry configured to compute a first signature based on the data of the write request and append the first signature to the write request, before the write request is sent to the memory controller over the communication network; and
second processing circuitry configured to receive the write request having the appended first signature, from the communication network, compute a second signature based on the data of the write request, and compare the first signature appended to the write request data to the second signature.

2. The integrated circuit of claim 1 , wherein the second processing circuitry is further configured to request that the data be resent when the first signature appended to the write request differs from the second signature.

3. The integrated circuit of claim 1 , wherein the communication network comprises:
a packet-based network-on-chip (NoC).

4. The integrated circuit of claim 1 , wherein the first processing circuitry is further configured to:
compute first signatures for all data output from the data circuitry to the communication network.

5. The integrated circuit of claim 1 , wherein the memory controller comprises a portion of the second processing circuitry.

6. The integrated circuit of claim 1 , wherein the memory controller is further configured to populate a data transfer list with results of the comparison of the first signature appended to the write request and the second signature, and wherein the data transfer list comprises a listing of multiple sets of data to be transferred to the memory device.

7. The integrated circuit of claim 6 , wherein the memory controller is further configured to populate a header of the data transfer list with the results of the comparison.

8. The integrated circuit of claim 7 , wherein the memory controller is further configured to selectively perform the comparison of the first signature appended to the data and the second signature based on a value of a signature enable field of the data transfer list.

9. The integrated circuit of claim 1 , wherein:
the second processing circuitry is further configured to detect a read response from the memory controller, compute a third signature based on data of the read response, append the third signature to the read response, and forward the read response with the appended third signature to the data circuitry over the communication network; and
the first processing circuitry is further configured to detect the read response at an input of the data circuitry, compute a fourth signature based on the data of the read response, and compare the third signature appended to the read response to the fourth signature.

10. An integrated circuit, comprising:
a first communication path;
data circuitry configured to send a read request over the first communication path;
a memory controller configured to receive the read request from the first communication path, retrieve corresponding read response data from a memory device, and send the read response data to the data circuitry over the first communication path;
first processing circuitry configured to compute a first signature based on the read response data and append the first signature to the read response data, before the read response data is sent to the data circuitry over the first communication path; and
second processing circuitry configured to receive the read response data having the appended first signature, from the first communication path, compute a second signature based on the read response data, and compare the second signature to the first signature appended to the read response data.

11. The integrated circuit of claim 10 , wherein:
the first communication path comprises a network-on-chip (NoC).

12. The integrated circuit of claim 10 , wherein:
the second processing circuitry is further configured to initiate resending the read response data when the first signature appended to the read response data differs from the second signature.

13. The integrated circuit of claim 10 , wherein the data circuitry comprises a field-programmable gate array (FPGA) configured to interface with an external sensor based on a protocol a protocol that provides packet level data protection.

14. The integrated circuit of claim 13 , wherein the external sensor comprises a vehicle sensor-data circuitry.

15. The integrated circuit of claim 14 , wherein the vehicle sensor comprises a camera.

16. The integrated circuit of claim 13 , further comprising:
a second communication path; and
a processor subsystem configured to interface with the FPGA based on the protocol that provides the packet level data protection, and to send additional read requests to the memory controller over the second communication path;
wherein the memory controller is further configured to retrieve additional read response data from the memory device based on the additional read requests, and send the additional read response data to the processor subsystem over the second communication path;
wherein the first processing circuitry is further configured to compute signatures of the additional read response data and append the signatures to the respective additional read response data before the additional read response data is sent to the processor subsystem over the second communication path; and
wherein the second processing circuitry is further configured to receive the additional read response data having the appended signatures, from the second communication path, compute additional signatures based on the additional read response data, and compare the additional signatures to the signatures appended to the respective additional read response data.

17. A method comprising:
detecting a write request output by data circuitry of an integrated circuit device, by first processing circuitry;
computing a first signature based on data of the write request, by the first processing circuitry;
appending the first signature to the write request, by the first processing circuitry;
forwarding the write request and the appended first signature over a communication network to a memory controller of the integrated circuit device;
detecting the write request having the appended first signature at an input of the memory controller, by second processing circuitry;
computing a second signature based on the data of the write request, by the second processing circuitry; and
comparing the second signature to the first signature appended to the write request, by the second processing circuitry.

18. The method of claim 17 , further comprising:
computing first signatures for all data sent from the data circuitry to the communication network and appending the first signatures to the respective data, before the data is transmitted over the communication network.

19. The method of claim 17 , further comprising:
detecting a read response from the memory controller, by the second processing circuitry;
computing a third signature based on data of the read response, by the second processing circuitry;
appending the third signature to the read response, by the second processing circuitry;
forwarding the read response with the appended third signature to the data circuitry over the co

Assignees

• Xilinx Inc

Inventors

• Bhardwaj Pramod
• Azad Sarosh I
• Koe Wern-Yan
• Majumdar Amitava

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title