Transceiver loopback testing

Patent metadata

Field	Value
Publication number	US-2025211341-A1
Application number	US-202318393151-A
Country	US
Kind code	A1
Filing date	Dec 21, 2023
Priority date	Dec 21, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

First claim

What is claimed is:

1 . A transceiver circuit, comprising:
a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data; a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, wherein the serializer circuit comprises a serializer data storage device, and wherein the serializer data storage device lacks circuit structures for scanability; a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, wherein the deserializer circuit comprises a deserializer data storage device, and wherein the deserializer data storage device lacks circuit structures for scanability; and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

2 . The transceiver circuit of claim 1 , wherein the serialized data forms a first sequence of bit values, wherein the serial receiver data received by the deserializer circuit forms a second sequence of bit values, and wherein the first sequence of bit values is equal to the second sequence of bit values.

3 . The transceiver circuit of claim 1 , wherein the serial receiver data received by the deserializer circuit is generated based at least in part on an analog signal, and wherein the analog signal is generated based at least in part on the serialized data.

4 . The transceiver circuit of claim 1 , wherein the first register circuit is configured to receive a test pattern, and to recirculate the test pattern according to a test standard.

5 . The transceiver circuit of claim 1 , wherein the deserializer circuit is configured to receive the serial data in response to a first clock signal having a first frequency, wherein the deserializer circuit is configured to generate the multi-bit parallel response data in response to a second clock signal having a second frequency, wherein the second frequency is less than the first frequency.

6 . The transceiver circuit of claim 1 , wherein the serializer circuit is configured to generate the serialized data in response to a first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to a second clock signal, and wherein the first and second clock signals are both derived from a single third clock signal.

7 . The transceiver circuit of claim 6 , wherein the serializer circuit is configured to generate the serialized data in response to the first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to the second clock signal, and wherein the first and second clock signals have a phase difference controlled at least in part by a delay of a delay circuit.

8 . The transceiver circuit of claim 1 , further comprising:
a first resettable clock circuit configured to generate a first clock signal; and a second resettable clock circuit configured to generate a second clock signal, wherein the first and second resettable clock circuits are configured to be reset with a scan enable signal, wherein the serializer circuit is configured to generate the serialized data in response to the first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to the second clock signal, and wherein the first register circuit is configured to receive the serial stimulus data in response to the scan enable signal.

9 . A system, comprising:
a controller; and a transceiver circuit, comprising:
a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data;
a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, wherein the serializer circuit comprises a serializer data storage device, and wherein the serializer data storage device lacks circuit structures for scanability;
a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, wherein the deserializer circuit comprises a deserializer data storage device, and wherein the deserializer data storage device lacks circuit structures for scanability; and
a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data,
wherein the controller is configured to provide the serial stimulus data to the first register circuit with a first scan operation, and wherein the controller is configured to receive the serial response data from the second register circuit in a second scan operation.

10 . The system of claim 9 , wherein the serialized data forms a first sequence of bit values, wherein the serial data received by the deserializer circuit forms a second sequence of bit values, and wherein the first sequence of bit values is equal to the second sequence of bit values.

11 . The system of claim 9 , wherein the serial receiver data received by the deserializer circuit is generated based at least in part on an analog signal, and wherein the analog signal is generated based at least in part on the serialized data.

12 . The system of claim 9 , wherein the first register circuit is configured to receive a test pattern, and to recirculate the test pattern according to a test standard.

13 . The system of claim 9 , wherein the deserializer circuit is configured to receive the serial receiver data in response to a first clock signal having a first frequency, wherein the deserializer circuit is configured to generate the multi-bit parallel response data in response to a second clock signal having a second frequency, wherein the second frequency is less than the first frequency.

14 . The system of claim 9 , wherein the serializer circuit is configured to generate the serialized data in response to a first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to a second clock signal, and wherein the first and second clock signals are both derived from a single third clock signal.

15 . The system of claim 14 , wherein the serializer circuit is configured to generate the serialized data in response to the first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to the second clock signal, and wherein the first and second clock signals have a phase difference controlled at least in part by a delay of a delay circuit.

16 . The system of claim 9 , the transceiver circuit further comprising:
a first resettable clock circuit configured to generate a first clock signal; and a second resettable clock circuit configured to generate a second clock signal, wherein the first and second resettable clock circuits are configured to be reset with a scan enable signal, wherein the serializer circuit is configured to generate the serialized data in response to the first clock signal, wherein the deserializer circuit is configured to receive the serial receiver data in response to the second clock signal, and wherein the first register circuit is configured to receive the serial stimulus data in response to the scan enable signal.

17 . A method of testing a transceiver circuit, the method comprising:
with a controller, asser

Assignees

• Xilinx Inc

Inventors

• Nerukonda Rambabu
• Ding Weiqi
• Majumdar Amitava
• Nair Bhuvanachandran K

Classifications

• H04B17/16

  Test equipment located at the transmitter · CPC title

• H04B17/0085 Primary

  using test signal generators · CPC title