Finite time counting period counting of infinite data streams

Patent metadata

Field	Value
Publication number	US-12217824-B2
Application number	US-202318160292-A
Country	US
Kind code	B2
Filing date	Jan 26, 2023
Priority date	Jan 27, 2022
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

First claim

What is claimed is:

1. An apparatus, comprising:
two tables stored in memory, each table configured to store an identical number of counters;
circuitry configured to:
receive consecutive periodic signals of a first type at a regular fixed interval during a monitoring duration;
reset one, but not the other, of the two tables in response to each of a first signal of the consecutive periodic signals and every alternate signal of the consecutive periodic signals occurring after the first signal, and reset the other, but not the one, of the two tables in response to a second signal of the consecutive periodic signals and every alternate signal of the consecutive periodic signals occurring after the second signal, wherein the first signal and the second signal are consecutive signals;
increment a corresponding counter in each of the two tables in response to each second type of signal received during the monitoring duration;
generate a third type of signal when any one of the counters exceeds a predetermined threshold during the monitoring duration.

2. The apparatus according to claim 1 , wherein the memory is a content addressable memory (CAM).

3. The apparatus according to claim 1 , wherein the memory is a static random access memory (SRAM).

4. The apparatus according to claim 1 , wherein the first type of signal is a reset signal, the second type of signal is a row access request or row access request indication received from a memory controller connected to a memory media device, and the third type of signal is a row hammer response or row hammer response generation request.

5. The apparatus according to claim 4 , wherein the total number of counters in the plurality of counters is less than a total number of rows monitored by a memory error detector on the memory media device.

6. The apparatus according to claim 5 , wherein each counter in the plurality of counters corresponds to a respective row monitored by a memory error detector on the memory media device.

7. The apparatus according to claim 5 , wherein each counter in the plurality of counters corresponds to a plurality of rows monitored by a memory error detector on the memory media device.

8. The apparatus according to claim 7 , wherein each counter in the plurality of counters corresponds to a same number of rows in the plurality of rows monitored by a memory error detector on the memory media device.

9. The apparatus according to claim 4 , wherein the circuitry is further configured to, when said any one of the counters exceeds the predetermined threshold, initialize said any one of the counters.

10. The apparatus according to claim 9 , wherein initializing comprises setting the any one of the counters to a minimum value of all counters in the plurality of counters.

11. The apparatus according to claim 9 , wherein the circuitry is further configured to, when said any one of the counters exceeds the predetermined threshold, initialize said any one of the counters by setting the any one of the counters to zero and setting a flag associated with the any one of the counters, wherein the flag indicates that the any one of the counters is dedicated to a row of the memory media device currently associated with the any one of the counters.

12. The apparatus according to claim 11 , wherein the circuitry is further configured to, in response to receiving the second type of signal, identifying a counter corresponding to a row associated with the second type of signal in the plurality of counters and incrementing the identified counter.

13. The apparatus according to claim 11 , wherein the circuitry is further configured to, in response to receiving the second type of signal, determining whether a counter corresponding to a row associated with the second type of signal is present in the plurality of counters and, when the determining determines that the counter corresponding to the row associated with the second type of signal is not present, inserting the counter into the plurality of counters and incrementing the counter.

14. The apparatus according to claim 13 , wherein the circuitry is further configured to, in response to a determining that the plurality of counters are at a maximum, evicting a counter from the plurality of counters to enable the inserting.

15. The apparatus according to claim 14 , wherein the evicting comprises identifying a minimum counter in the plurality of counters and evicting the minimum counter.

16. The apparatus according to claim 1 , wherein an input of each of the two tables is connected to a respective AND circuit, and a first input to each respective AND circuit is connected to a flip-flop circuit and a second input of each respective AND circuit is connected to an interval counter.

17. The apparatus according to claim 16 , further comprising a third AND circuit connected to an output of the first of the two tables and to an output of the flip-flop circuit and a fourth AND circuit connected to an output of a second of the two tables and to an output of the flip-flop circuit.

18. The apparatus according to claim 17 , wherein the third AND circuit and the fourth AND circuit are configured to select one of the third type of signals generated by the first table and the second table.

19. The apparatus according to claim 16 , further comprising an OR circuit connected to an output of each of the two tables, wherein the OR circuit configured to select one of the third type of signals generated by the two tables.

20. A method comprising:
receiving consecutive periodic signals of a first type at a regular fixed interval during a monitoring duration;
resetting one, but not the other, of two tables in response to each of a first signal of the consecutive periodic signals and every alternate signal of the consecutive periodic signals occurring after the first signal, and reset the other, but not the one, of the two tables in response to a second signal of the consecutive periodic signals and every alternate signal of the consecutive periodic signals occurring after the second signal, wherein the first signal and the second signal are consecutive signals, and wherein the two tables are stored in memory and each table is configured to store an identical number of counters;
incrementing a corresponding counter in each of the two tables in response to each second type of signal received during the monitoring duration;
generating a third type of signal when any one of the counters exceeds a predetermined threshold during the monitoring duration.

Assignees

• Micron Technology Inc

Inventors

• Gieske Edmund
• Majumdar Amitava
• Dirik Cagdas
• Ayyapureddi Sujeet
• Lu Yang
• Akel Ameen D
• Caraccio Danilo
• Izzo Niccolo′
• Cooper-Balis Elliott C
• Geiger Markus H

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title