Memory device security and row hammer mitigation

Patent metadata

Field	Value
Publication number	US-2024411466-A1
Application number	US-202418808887-A
Country	US
Kind code	A1
Filing date	Aug 19, 2024
Priority date	Jun 2, 2022
Publication date	Dec 12, 2024
Grant date	—

Abstract

Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

First claim

1 .- 20 . (canceled)

21 . A method, comprising:
receiving a row activation command having a row address at control circuitry of a memory sub-system; incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system; determining, at the control circuitry, whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); and responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM.

22 . The method of claim 1 , further comprising, responsive to determining that the first count is greater than the RHT minus the second count, deleting the row counter corresponding to the row address from the CAM.

23 . The method of claim 1 , further comprising initializing a plurality of CDCs including the CDC to 0 prior to receipt of the row activation command.

24 . The method of claim 1 , wherein incrementing the first count of the row counter includes incrementing the first count of the row counter responsive to determining that the row counter is stored in the CAM.

25 . The method of claim 1 , further comprising setting a size of the CAM based on a frequency target for row activation commands.

26 . The method of claim 1 , further comprising setting the size of the CAM based on a frequency target for row activation commands that is less than the RHT.

27 . The method of claim 1 , further comprising setting a size of the CAM based on a maximum quantity of row activations for a particular period.

28 . An apparatus, comprising:
a content addressable memory (CAM); a memory device; and control circuitry coupled to the memory device and configured to:
receive a row activation command having a row address of the memory device;
responsive to determining that a row counter corresponding to the row address is stored in the CAM, increment a first count of the row counter;
determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); and
responsive to determining that the first count is greater than the RHT minus the second count:
issue a refresh command to the row address; and
delete the row counter corresponding to the row address from the CAM.

29 . The apparatus of claim 8 , wherein the control circuitry is further configured to determine whether the CAM has space to store the row counter responsive to determining that the row counter is not stored in the CAM.

30 . The apparatus of claim 9 , wherein the control circuitry is further configured to, responsive to determining that the CAM has space to store the row counter, store the row counter in the CAM.

31 . The apparatus of claim 9 , wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, decrement a plurality of counts of the CAM including the first count.

32 . The apparatus of claim 11 , wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, delete any of the plurality of counts that have a zero value to unassociated a particular row corresponding to a deleted count with the CAM.

33 . The apparatus of claim 11 , wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the counter, increment the second count of the CDC.

34 . An apparatus, comprising:
a content addressable memory (CAM); a memory device; control circuitry coupled to the memory device and configured to:
receive a row activation command directed to a row address of the memory device;
determine whether a row counter corresponding to the row address is stored in the CAM;
responsive to determining that the row counter is not stored in the CAM and to determining that the CAM is full:
decrement a plurality of row counters stored in the CAM; and
increment a second count of a CAM decrease counter (CDC);

responsive to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than a difference between a row hammer threshold (RHT) and the second count of the CDC; and
responsive to determining that the first count is greater than the difference between the RHT and the second count, issue a refresh command to the row address.

35 . The apparatus of claim 14 , wherein the control circuitry is further configured to delete the row counter corresponding to the row address from the CAM responsive to determining that the first count is greater than the difference between the RHT and the second count.

36 . The apparatus of claim 14 , wherein the control circuitry is further configured to, subsequent to determining that the row counter corresponding to the row address is not stored in the CAM, determine whether the CAM has space to store the row counter.

37 . The apparatus of claim 16 , wherein the control circuitry is further configured to, responsive to determining that the CAM does not have space to store the row counter, decrement a plurality of counts of a plurality of row counters stored in the CAM.

38 . The apparatus of claim 17 , wherein the control circuitry is further configured to, responsive to decrementing the plurality of counts, determine whether any of the plurality of counts is equal to 0.

39 . The apparatus of claim 18 , wherein the control circuitry is further configured to, responsive to determining that at least one count of the plurality of row counts is equal to 0, delete a corresponding row counter from the CAM.

40 . The apparatus of claim 18 , wherein the control circuitry is further configured to, responsive to deleting the corresponding row counter the CAM, incrementing the second count of the CDC.

Assignees

• Micron Technology Inc

Inventors

• Lu Yang
• Ayyapureddi Sujeet
• Gieske Edmund J
• Dirik Cagdas
• Akel Ameen D
• Cooper-Balis Elliott C
• Majumdar Amitava
• Walker Robert M
• Caraccio Danilo

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G11C15/04

  using semiconductor elements · CPC title