Instant write scheme with delayed parity/raid

Patent metadata

Field	Value
Publication number	US-12019516-B2
Application number	US-202217894886-A
Country	US
Kind code	B2
Filing date	Aug 24, 2022
Priority date	Jan 24, 2022
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.

First claim

What is claimed is:

1. A memory system comprising:
a plurality of memory channels, each having a parity bit;
a redundant array of independent devices (RAID) parity channel; and
a controller of the memory system configured to:
receive a block of data for storage in the memory channels;
determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low;
write the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data when the data traffic demand is low; and
only write the data for storage in the memory channels when the data traffic demand is high.

2. The memory system of claim 1 , wherein the updating is deferred upon determining the data traffic demand is high.

3. The memory system of claim 2 , wherein the memory channels comprise dynamic random access memory (DRAM) channels coupled with a plurality of DRAM chips, each being configured to store at least one of (i) a codeword comprising a set of data bytes and one or more parity bytes and (ii) a RAID byte.

4. The memory system of claim 1 , further comprising:
a lookup table (LUT) configured to store an indication that a parity data was updated during a prior write operation or was not updated during the prior write operation.

5. The memory system of claim 4 , wherein the controller is further configured to:
monitor the data traffic to identify when the data traffic is low subsequent to only writing the data for storage in the memory channels;
read the LUT to determine which parity bits are not set when the data traffic demand is low;
read the channels with the data associated with the unset parity bits when the parity bits are not set;
calculate the parity bits and the raid parity byte for the block of data; and
write the calculated parity bits and the calculated RAID parity byte to the parity bits and RAID parity byte.

6. The memory system of claim 5 , wherein the controller is configured to calculate the parity bits and the RAID parity byte, the updated parity encompassing multiple prior write operations.

7. The memory system of claim 1 , wherein the controller is configured to determine the memory traffic demand as being high or low based on a threshold value for current or recent memory demand.

8. The memory system of claim 7 , wherein the threshold value comprises a percentage of a memory write request queue currently occupied with write requests.

9. The memory system of claim 1 , wherein the controller comprises a compute express link (CXL) controller.

10. The memory controller of claim 1 , further comprising a cache memory configured to buffer memory writes between a host processor and the plurality of memory channels.

11. The memory system of claim 1 , further comprising:
a First-in-First-out (FIFO) outdated parity stack (OPS) configured to store an address of an outdated parity data, thereby indicating when the parity data was not updated during a prior write operation.

12. A method comprising:
receiving at a memory system a block of data for storage in a plurality of memory channels of the memory system;
determining via a controller of the memory system when a data traffic demand on a plurality of memory channels is high or when a data traffic demand on the plurality of memory channels is low;
writing the block of data for storage in the memory channels, and concurrently updating a respective parity bit of each memory channel and updating a redundant array of independent devices (RAID) parity channel of the plurality of memory channels when the data traffic demand is low; and
only writing the data for storage in the memory channels when the data traffic demand is high.

13. The method of claim 12 , wherein the update of the parity bits and the RAID parity channel for the stored block of data is deferred.

14. The method of claim 12 , wherein writing the block of data for storage in the memory channels comprises writing the memory data into a plurality of DRAM chips, each being configured to store at least one of (i) a codeword comprising a set of data bytes and one or more parity bytes and (ii) a RAID byte.

15. The method of claim 12 , further comprising:
storing in a lookup table (LUT) of the memory system either an indication that a parity data was updated during a prior write operation or an indication that the parity data was not updated during the prior write operation.

16. The method of claim 15 , further comprising:
subsequent to only writing the data for storage in the memory channels only, while deferring the update of the parity bits and the RAID parity channel, monitoring via the controller the data traffic to identify when the data traffic is low;
reading the LUT to determine which parity bits are not set when the data traffic demand is low;
reading the channels with the data associated with the unset parity bits upon determining which parity bits are not set;
calculating the parity bits and the raid parity byte for the block of data; and
writing the calculated parity bits and the calculated RAID parity byte to the parity bits and RAID parity byte.

17. The method of claim 16 , further comprising calculating the parity bits and the RAID parity byte so that the updated parity encompasses multiple prior write operations.

18. The method of claim 12 , further comprising determining via the controller that the memory traffic demand is high or low based on a threshold value for current or recent memory demand.

19. The method of claim 18 , wherein determining the threshold value comprises determining a percentage of a memory write request queue which is currently occupied with write requests.

20. The method of claim 12 , further comprising buffering memory write requests from a host processor in a cache memory for retrieval by the plurality of memory channels.

21. The method of claim 12 , further comprising:
storing in a First-in-First-out (FIFO) outdated parity stack (OPS) of the memory system an address of outdated parity, and
upon sending an update parity command to the memory channels, retrieving the oldest address in the OPS FIFO and updating the corresponding parity.

22. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory system, causes the memory system to:
receiving a block of data for storage in a plurality of memory channels of the memory system;
determine when a data traffic demand on the plurality of memory channels is high and when a data traffic demand on the plurality of memory channels is low;
write the block of data for storage in the memory channels, and concurrently update a respective parity bit of each memory channel and update a reductant array of independent devices (RAID) parity channel of the plurality of memory channels when the data traffic demand is low; and
only write the data for storage in the memory channels when the data traffic demand is high.

Assignees

• Micron Technology Inc

Inventors

• Yang Lingming
• Majumdar Amitava
• Thirumala Sandeep Krishna
• Gajera Nevil

Classifications

• G06F11/1096

  Parity calculation or recalculation after configuration or reconfiguration of the system · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title