Deterministic built-in self-test

Patent metadata

Field	Value
Publication number	US-2025292853-A1
Application number	US-202418608175-A
Country	US
Kind code	A1
Filing date	Mar 18, 2024
Priority date	Mar 18, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

Embodiments herein describe a computer architecture including a device having a test vector memory (TVM) space configured to store test patterns and a deterministic built-in self-test (DBIST) direct memory access (DMA) controller configured to receive the test patterns directly from the TVM space and apply the test patterns to at least one hardware block under test. The DBIST DMA controller sends a scan bus signal and a scan clock signal to the at least one hardware block under test, the scan bus signal providing the test patterns to the at least one hardware block under test. The test patterns are generated by a manufacturer of the at least one hardware block under test.

First claim

1 . A computer architecture comprising:
a device having:
a test vector memory (TVM) space configured to store pre-generated test patterns; and
a deterministic built-in self-test (DBIST) direct memory access (DMA) controller configured to receive the pre-generated test patterns directly from the TVM space and apply the pre-generated test patterns, using a scan bus, to at least one hardware block under test during in-field testing.

2 . The computer architecture of claim 1 , wherein the DBIST DMA controller sends a scan bus signal from the scan bus and a scan clock signal to the at least one hardware block under test.

3 . The computer architecture of claim 2 , wherein the scan bus signal provides the pre-generated test patterns to the at least one hardware block under test.

4 . The computer architecture of claim 1 , wherein the device is part of a field-programmable gate array (FPGA).

5 . The computer architecture of claim 1 , wherein the pre-generated test patterns are generated during manufacturing at a manufacturing facility and stored in an uncompressed format.

6 . The computer architecture of claim 1 , wherein a DFx lockout circuit is configured to prevent access to the at least one hardware block under test on a programmable security setting.

7 . The computer architecture of claim 1 , wherein the DBIST DMA controller communicates directly with the TVM space via an interconnection network.

8 . The computer architecture of claim 1 , wherein the pre-generated test patterns include hundreds of test patterns.

9 . The computer architecture of claim 1 , wherein the pre-generated test patterns are generated by a manufacturer of the at least one hardware block under test.

10 . The computer architecture of claim 1 , wherein the at least one hardware block under test is coupled to a plurality of other hardware blocks, and wherein the plurality of other hardware blocks remain functional during DBIST testing of the at least one hardware block.

11 . The computer architecture of claim 10 , wherein a system or device controller using firmware allows the plurality of other hardware blocks to remain functional during the DBIST testing of the at least one hardware block.

12 . The computer architecture of claim 10 , wherein output clamping logic allows the plurality of other hardware blocks to remain functional during the DBIST testing of the at least one hardware block.

13 . A method comprising:
using a device to:
store pre-generated test patterns in a test vector memory (TVM) space; and
allow a deterministic built-in self-test (DBIST) direct memory access (DMA) controller to receive the pre-generated test patterns directly from the TVM space and apply the pre-generated test patterns, using a scan bus, to at least one hardware block under test during in-field testing.

14 . The method of claim 13 , wherein the DBIST DMA controller sends a scan bus signal from the scan bus and a scan clock signal to the at least one hardware block under test, the scan bus signal providing the test patterns to the at least one hardware block under test.

15 . The method of claim 13 , wherein the device communicates with a system controller communicating with the at least one hardware block under test via a programming side channel.

16 . The method of claim 13 , wherein the DBIST DMA controller communicates directly with the TVM space via an interconnection network.

17 . The method of claim 13 , wherein the pre-generated test patterns are generated by a manufacturer of the at least one hardware block under test.

18 . The method of claim 13 , wherein the at least one hardware block under test is coupled to a plurality of other hardware blocks, and wherein the plurality of other hardware blocks remain functional during DBIST testing of the at least one hardware block.

19 . The method of claim 18 , wherein a system or device controller using firmware allows the plurality of other hardware blocks to remain functional during the DBIST testing of the at least one hardware block.

20 . The method of claim 18 , wherein output clamping logic allows the plurality of other hardware blocks to remain functional during the DBIST testing of the at least one hardware block.

Assignees

• Xilinx Inc

Inventors

• Majumdar Amitava
• Lin Albert Shih-Huai
• Chaudhuri Partho Tapan
• Bhardwaj Pramod
• Azad Sarosh I

Classifications

• G11C2029/3602

  Pattern generator · CPC title

• G11C29/38

  Response verification devices · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title