Row hammer telemetry

Patent metadata

Field	Value
Publication number	US-12131071-B2
Application number	US-202318121874-A
Country	US
Kind code	B2
Filing date	Mar 15, 2023
Priority date	Mar 15, 2022
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

First claim

What is claimed is:

1. An apparatus, comprising:
a number of memory devices; and
a memory controller coupled to one or more of the number of memory devices, the memory controller including a row hammer detector and being configured to:
increment for a first time period:
a row counter in a first data structure; and
a refresh counter based on a quantity of directed refresh management (dRFM) commands issued by the first data structure during the first time period;

increment for a second time period:
a row counter in a second data structure; and
the refresh counter based on a quantity of dRFM commands issued by the second data structure during the second time period;

determine that a value of the refresh counter exceeds a refresh threshold; and
responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

2. The apparatus of claim 1 , wherein the memory controller is further configured to periodically reset the refresh counter subsequent to elapse of the second time period, and wherein a duration of the first time period is equal to a duration of the second time period.

3. The apparatus of claim 1 , further comprising a counter buffer coupled to the refresh counter, and wherein the memory controller is further configured to:
store a value of the refresh counter in the counter buffer; and
subsequent to storage of the value of the refresh counter in the counter buffer, reset the refresh counter.

4. The apparatus of claim 1 , wherein the first data structure is a first content-addressable memory (CAM), and wherein the second data structure is a second CAM.

5. The apparatus of claim 1 , wherein the refresh counter is incremented for each dRFM command issued via the respective channel to memory banks of the number of memory devices, and wherein the refresh counter is incremented in the absence of storage of any specific address associated with each of the dRFM commands.

6. A method comprising:
receiving, at a memory controller of a memory sub-system, signaling indicative of an amount of row activations directed to a row of a memory device of the memory sub-system over a first time period and a second time period;
incrementing over the first time period:
a row counter in a first data structure; and
a refresh counter from a first value to a second value, wherein the second value represents quantities of directed refresh management (dRFM) commands issued by the first data structure via a respective channel to memory banks of the memory device;

incrementing over the second time period:
a row counter in a second data structure; and
the refresh counter from the second value to a third value, wherein the third value represents the respective quantity of dRFM commands issued by the first data structure and a quantity of dRFM commands issued by the second data structure via the respective channel to the memory banks of the memory device;

determining a value of the refresh counter exceeds a refresh threshold; and
responsive to the determination that the refresh threshold is exceeded, issuing a notification.

7. The method of claim 6 , further comprising resetting the refresh counter from the third value to the first value subsequent to elapse of the second time period.

8. The method of claim 7 , further comprising resetting the row counter in the first data structure.

9. The method of claim 8 , further comprising:
subsequent to incrementing the row counter in the second data structure, incrementing over a third time period:
the row counter in the first data structure from a first value to a second value; and
the refresh counter from the first value to a second value.

10. The method of claim 6 , further comprising resetting the row counter in the first data structure and the refresh counter subsequent to elapse of the first time period.

11. The method of claim 10 , further comprising resetting the row counter in the second data structure and the refresh counter subsequent elapse of the second time period.

12. The method of claim 6 , further comprising outputting the first value of the refresh counter, the second value of the refresh counter, or both, to a counter buffer.

13. The method of claim 12 , further comprising outputting the first value, the second value, or both, prior to resetting the refresh counter.

14. An apparatus, comprising:
a number of memory devices; and
a memory controller coupled to one or more of the number of memory devices, the memory controller including a row hammer detector and being configured to:
increment for a first time period:
a row counter in a first data structure; and
a first refresh counter to represent a quantity of directed refresh management (dRFM) commands issued by the first data structure to a memory bank during the first time period;

increment for a second time period:
a row counter in a second data structure; and
a second refresh counter to represent a quantity of dRFM commands issued by the second data structure to the memory bank during the second time period;

determine that an incremented value of the first refresh counter or an incremented value of the second refresh counter exceeds a refresh threshold; and
responsive to the determination that the refresh threshold is exceeded, issue a notification.

15. The apparatus of claim 14 , further comprising a first counter buffer coupled to the first refresh counter and a second counter buffer coupled to the second refresh counter, and wherein the memory controller is further configured to:
store the incremented value of the first refresh counter in the first counter buffer; and
subsequent to storage of the incremented value of the first refresh counter in the first counter buffer, reset the first refresh counter; and
increment for a third time period:
the row counter in the first data structure; and
the first refresh counter.

16. The apparatus of claim 14 , wherein:
the memory controller is further configured to periodically reset the incremented value of the first refresh counter and the incremented value of the second refresh counter; and
the memory controller is further configured to refresh the incremented value of the first refresh counter subsequent to elapse of an individual time period, and wherein the memory controller is further configured to periodically refresh the incremented value of the second refresh counter subsequent to elapse of two time periods.

17. The apparatus of claim 14 , wherein:
the first refresh counter and the second refresh counter are included in a plurality of refresh counters, and wherein the first data structure and the second data structure are included in a plurality of data structures, and wherein a quantity of the plurality of refresh counters is equal to a quantity of the plurality of data structures; and
the quantity of the plurality of the refresh counters is equal to at least a quantity of banks of memory in the number of memory devices, and wherein the quantity of the plurality of the refresh counters is equal to at least a quantity of channels in the number of memory devices.

18. The apparatus of claim 17 , wherein the quantity of the plurality of the refresh counters is equal to at least twice a quantity of banks of memory in the number of memory devices, and wherein the quantity of the plurality of the refresh counters is equal to at least twice a quantity of channels in the number of memory devices.

19. The apparatus of claim 14 , further comprising:
a first switch coupled to the first dat

Assignees

• Micron Technology Inc

Inventors

• Majumdar Amitava
• Nagendrakumar Anandhavel
• Hargan Mohammed Ebrahim
• Garner Scott
• Caraccio Danilo
• Balluchi Daniele
• Chang Chia Wei
• Lal Ankush

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title