Finite time counting period counting of infinite data streams

Patent metadata

Field	Value
Publication number	US-2025378864-A1
Application number	US-202519012470-A
Country	US
Kind code	A1
Filing date	Jan 7, 2025
Priority date	Jan 27, 2022
Publication date	Dec 11, 2025
Grant date	—

Abstract

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

First claim

What is claimed is:

1 . A system, comprising:
tables stored in a memory, each table configured to store an identical number of counters including first counters and second counters; circuitry configured to instruct the tables to concurrently count and operate in a ping-pong manner to be reset at times offset in relation to each other, wherein each table comprises a respective reset event spaced apart by a predetermine time interval from each other and continue in an active mode wherein each table is configured to generate row hammer responses or a request for row hammer responses during any particular time interval.

2 . The system according to claim 1 , wherein the memory is a content addressable memory (CAM).

3 . The system according to claim 1 , wherein the memory is a static random access memory (SRAM).

4 . The system according to claim 1 , wherein the circuitry comprises a plurality of AND circuits and a flip-flop circuit, and an input of each table is connected to a respective AND circuit, and a first input to each respective AND circuit is connected to a flip-flop circuit and a second input of each respective AND circuit is connected to an interval counter.

5 . The system according to claim 4 , wherein the circuitry further comprises an OR circuit connected to an output of each table, wherein the OR circuit is configured to select row hammer responses generated by the tables.

6 . The system of claim 5 , wherein an external clock provides an input clock and based on the input clock, the interval counter is configured to generate a pulse every predetermined time interval and based on the pulse generated the flip flop circuit is configured to toggle output between 0 and 1 every predetermined time interval and the first counters are reset when the second counters becomes active and vice versa.

7 . The system of claim 6 , wherein when both the first counters and the second counters receive and count memory media row activations and both the first counters and the second counters trigger row hammer responses when a memory media row hammer threshold count is reached and based on a state of the flip-flop circuit only one of the first counters and the second counters that is active triggers a row hammer response while the other of the first counters and the second counters is ignored, and the row hammer response or a request for the row hammer response is sent to a memory controller of the memory.

8 . The system of claim 7 , wherein in either of the tables, corresponding row activation counts in response to each received row access request is incremented, upon being notified by the memory controller, wherein when the first counters or the second counters corresponding to the received row access request is not in the tables, the corresponding first counters or the second counters is inserted to the tables with a starting value equal to a minimum value of any of the first counters and the second counters in the tables.

9 . The system of claim 7 , wherein when the tables are full, then the first counters or the second counters with a lowest value is evicted in favor of an insertion, and the tables are triggered by the row hammer response or request for row hammer response generated to update the first counters or the second counters corresponding to the generated row hammer response or request for row hammer response.

10 . The system of claim 7 , wherein the first counters or the second counters corresponding to an aggressor row is set to the minimum value of all first counters and second counters in the tables.

11 . The system of claim 10 , wherein the first counters or the second counters corresponding to the aggressor row is evicted from the tables.

Assignees

• Micron Technology Inc

Inventors

• Gieske Edmund
• Majumdar Amitava
• Dirik Cagdas
• Ayyapureddi Sujeet
• Lu Yang
• Akel Ameen D
• Caraccio Danilo
• Izzo Niccolo'
• Cooper-Balis Elliott C
• Geiger Markus H
• Walker Robert

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title