DFxNoC—a multi-protocol, multi-cast, and multi-root network-on-chip with dynamic resource allocation

Patent metadata

Field	Value
Publication number	US-12537521-B2
Application number	US-202318138008-A
Country	US
Kind code	B2
Filing date	Apr 21, 2023
Priority date	Apr 21, 2023
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.

First claim

What is claimed is:

1 . An integrated circuit (IC) device, comprising:
a plurality of end-points (EPs) that comprise functional circuitry; first and second root devices; an interconnect comprising configurable multi-port switch circuits and links amongst the multi-port switch circuits, the first root device, and the EPs; and control circuitry configured to:
configure the first root device and a first subset of the EPs, via a dedicated parameter path, to communicate with one another based on a first one of multiple protocols, and configure the multi-port switch circuits, via the dedicated parameter path, to provide first data transmit paths, first data response paths, and first clock paths between the first root device and the first subset of the EPs; and
configure the second root device and a second subset of the EPs, via the dedicated parameter path, to communicate with one another based on a second one of the protocols, and configure the multi-port switch circuits, via the dedicated parameter path, to provide second data transmit paths, second data response paths, and second clock paths between the second root device and the second subset of the EPs;
wherein the first root device is configured to provide first data and a first clock to the first subset of the EPs via the first data transmit paths and the first clock paths, respectively, and to receive first response data from the first subset of the EPs via the first data response paths; and wherein the second root device is configured to provide second data and a second clock to the second subset of the EPs via the second data transmit paths and the second clock paths, respectively, and to receive second response data from the second subset of the EPs via the second data response paths.

2 . The IC device of claim 1 , wherein:
the interconnect further comprises a multi-bit bus; and the control circuitry is further configured to allocate a first subset of bits of the multi-bit bus for the first data transmit paths and to allocation a second subset of bits of the multi-bit bus for the first data response paths.

3 . The IC device of claim 1 , wherein a first one of the multi-port switch circuits comprises a first port configured to receive the first data and the first clock, and a second port, and wherein the first multi-port switch circuit comprises:
synchronous output circuitry configured to output the first data received at the first port, synchronous with the first clock; bypass output circuitry configured to output the first data received at the first port, asynchronously with the first clock; and circuitry configured to provide the output of a selectable one of the synchronous output circuitry and the bypass output circuitry to the second port.

4 . The IC device of claim 1 , further comprising interface circuitry configured to interface between a first one of the multi-port switch circuits and a first one of the EPs, wherein the first multi-port switch circuit comprises first and second ports, and wherein:
the first port comprises an N-bit data input configured to receive the first data, and a clock input configured to receive the first clock, wherein N is a positive integer; the second port is configured to output the first data to the interface circuitry over an N-bit data link, synchronous with the first clock, and to output the first clock to the interface circuitry; the interface circuitry comprises first frequency converter circuitry configured to alter a data rate of the first data received over the N-bit data link by a factor of K to provide K×n bits of data at the altered data rate, wherein K and n are positive integers; and the interface circuitry further comprises input permutation circuitry configured to assign a selectable subset of n-bits of the K×n bits of data to the first EP over an n-bit data link at the altered data rate.

5 . The IC device of claim 4 , wherein the interface circuitry further comprises:
input delay circuitry that is configurable to delay the n-bits of data by a selectable number of cycles of the first clock.

6 . The IC device of claim 4 , wherein interface circuitry further comprises:
output permutation circuitry comprising an m-bit input configured to receive m-bit response data from the first EP, a K×m-bit output, wherein the output permutation circuitry is dynamically configurable to assign the m-bit response data to a selectable subset of the K×m-bit output; and second frequency conversion circuitry configured to alter a data rate of the K×m-bit output of the output of the output permutation circuitry by the factor K to convert the K×m-bit output of the permutation circuitry to M-bit response data having the altered data rate.

7 . The IC device of claim 6 , wherein:
the output permutation circuitry further comprises circuitry configured to set unselected bits of the K×m-bit output of the permutation circuitry to a predetermined state; the second port of the first multi-port switch circuit is configured to receive the M-bit response data from the interface circuit; and the first port of the first multi-port switch circuit further comprises circuitry configured to merge the M-bit response data with M-bit response data received at one or more other ports of the first multi-switch circuit.

8 . The IC device of claim 6 , wherein the interface circuitry further comprises:
output delay circuitry that is configurable to delay the m-bits response data by a selectable number of cycles of the first clock.

9 . The IC device of claim 1 , wherein:
the first data comprises loopback data; and the interconnect further comprises loop-back circuitry that is dynamically configured to route the loopback data to the first root device.

10 . The IC device of claim 1 , further comprising a second root device, wherein a first one of the multi-port switch circuits comprises:
a first port that comprises a first clock input configured to receive the first clock; a second port that comprises a second clock input configured to receive the second clock; and clock selection circuitry configured to provide a selectable one of the first and second clocks to a clock output of the first multi-port switch circuit.

11 . The IC device of claim 1 , wherein the interconnect is configured to simultaneously route the first and second clocks and the first and second data to the respective first and second subsets of the EPs.

12 . The IC device of claim 1 , wherein:
the control circuitry is further configured to configure the first root device and a third subset of the EPs, via the dedicated parameter path, to communicate with one another based on a third one of the protocols, and re-configure the multi-port switch circuits, via the dedicated parameter path, to provide third second data transmit paths, third data response paths, and third clock paths between the first root device and the third subset of the EPs; and the first root device is further configured to provide third data and a third clock to the third subset of EPs via the third data transmit paths and the third clock paths, respectively, and to receive third response data from the third set of EPs via the third clock paths.

13 . The IC device of claim 1 , wherein the first root device comprises:
multiple protocol engines, each comprising circuitry configured to format data based on a respective one of the protocols; stimulus derivation circuitry configured to output the formatted data of a selectable one of the protocol engines to the interconnect; and response derivation circuitry configured to receive the first response data from the interconnect, and provide the first resp

Assignees

• Xilinx Inc

Inventors

• Nerukonda Rambabu
• Lin Albert Shih-Huai
• Borra Sreedhar
• Chadha Rajat
• Majumdar Amitava

Classifications

• H04L12/40

  Bus networks · CPC title

• G06F15/17312

  Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion (routing on a LAN H04L45/00) · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H03K17/56 Primary

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title