Error detection, correction, and media management on a memory device

Patent metadata

Field	Value
Publication number	US-12347512-B2
Application number	US-202318169621-A
Country	US
Kind code	B2
Filing date	Feb 15, 2023
Priority date	Sep 21, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

First claim

What is claimed is:

1. A memory system, comprising:
a transaction layer configured to interface with a host processor;
a memory controller with a physical layer configured to interface with a dynamic random-access memory (DRAM);
an error logic block (ELB) configured to identify a data read error in a data block read from DRAM and provide error correction for the data read error from the DRAM data block;
a persistent storage configured to store a historical record of memory addresses which have displayed data read errors; and
a post-package repair (PPR) logic block configured to:
identify all of: (a) whether the data read error indicates a requirement for a post-package repair (PPR) of the data block memory address where the data read error occurred, (b) whether a required repair is a soft PPR or a hard PPR, (c) whether a PPR resource is available for a required soft PPR or hard PPR, and (d) whether to make a soft PPR or a hard PPR based on the required repair and the available PPR resource; and
perform the post-package repair.

2. The memory system of claim 1 , wherein:
the memory controller and physical layer are configured to read the data block from a first memory address of the DRAM;
the ELB is configured to identify an error in the data block;
the ELB is further configured to correct the error to generate a corrected data;
the PPR logic block is configured to:
write the corrected data back to the first memory address;
read the data back from the first memory address to obtain a read-back data;
identify whether the read-back data has an error or not;
upon determining the read-back data has a memory error:
identify that the first memory address is in need of repair;
upon identifying that the first memory address is in need of repair, repair the first memory address;
record a location of the memory error in a long-term historical storage of memory errors; and

upon determining that the read-back data does not have an error, determine that the first memory address has a history of read errors or that the first memory address does not have a history of read errors.

3. The memory system of claim 2 , wherein the PPR logic block is further configured that upon determining that the read-back data does not have an error, and that the first memory address does have a history of read errors, the PPR logic block identifies that the first memory address is in need of repair or that the first memory address is not in need of repair; and
the PPR logic block records the location of the memory error in the long-term historical storage of memory errors.

4. The memory system of claim 3 , wherein the PPR logic block identifies the first memory address is in need of repair or the first memory address is not in need of repair by:
identifying from the long-term historical storage of memory errors at least one of: a number of historical memory errors for the first memory address and a time frequency of historical memory errors for the first memory address; and
determining the first memory address is in need of repair upon at least one of: the number of historical memory errors exceeds a designated error threshold and the time frequency of historical memory errors exceeds a designated frequency threshold.

5. The memory system of claim 2 , wherein the PPR logic block is configured so that upon determining that the first memory address is in need of repair, the PPR logic block performs either a soft post package repair or a hard post package repair.

6. The memory system of claim 2 , wherein the PPR logic block is configured so that repairing the first memory address further comprises performing either a soft post package repair or a hard post package repair.

7. A post-packaging repair (PPR) logic processor of a memory system, comprising:
a communicative coupling with a dynamic random access memory (DRAM) controller, wherein the PPR logic processor is configured to send data blocks to and receive data blocks from the DRAM;
a communicative coupling with an error logic block (ELB) of the DRAM controller; and
a communicative coupling with a persistent storage of the DRAM controller;
wherein the PPR logic processor is configured to:
receive from the ELB an indication that an error was found in a first data block read from the DRAM;
receive from the ELB a corrected data, said corrected data being written back to the first data block by the memory system;
read the data back from a memory address of the first data block to obtain a read-back data;
identify that the read-back data has an error or that the read-back data does not have an error;
upon determining that the read-back data has a memory error, identifying that the first memory address is in need of repair;
upon identifying that the first memory address is in need of repair, repairing the first memory address; and
recording an address of the memory error in a long-term historical storage of memory errors in the persistent storage; and
upon determining that the read-back data does not have an error, determining that the first memory address has a history of read errors or that the first memory address does not have a history of read errors.

8. The PPR logic processor of claim 7 , wherein the PPR logic processor is further configured that upon determining that the read-back data does not have an error, and that the first memory address does not have a history of read errors, the PPR logic processor records the address of the memory error in the long-term historical storage or memory errors.

9. The PPR logic processor of a claim 7 , wherein the PPR logic processor is further configured that upon determining that the read-back data does not have an error, and that the first memory address does have a history of read errors, PPR logic processor identifies that the first memory address is in need of repair or that the first memory address is not in need of repair; and
recording a location of the memory error in the long-term historical storage of memory errors.

10. The PPR logic processor of a claim 7 , wherein the PPR logic processor is further configured that upon identifying that the first memory address is in need of repair or that the first memory address is not in need of repair, the PPR logic processor further identifies from the long-term historical storage of memory errors at least one of: a number of historical memory errors for the first memory address and a time frequency of historical memory errors for the first memory address; and
determines that the first memory address is in need of repair based upon at last one of: the number of historical memory errors exceeding a designated error threshold and the time frequency of historical memory errors exceeding a designated time frequency threshold.

11. The PPR logic processor of a claim 7 , wherein the PPR logic processor is further configured that upon determining that the first memory address is in need of repair, the PPR logic processor performs either a soft post package repair or a hard post package repair.

12. The PPR logic processor of a claim 7 , wherein the PPR logic processor is further configured so that repairing the first memory address further comprises performing either a soft post package repair or a hard post package repair.

13. A persistent storage module comprising:
a communicative coupling to a central controller of a CXL drive; and
a long-term historical error storage;
wherein the persistent storage module is configured to:
receive from the central controller error data pertaining to read errors in memory read operations from a dynamic random access memory (DRAM) accessed by the central controller;
store

Assignees

• Micron Technology Inc

Inventors

• Majumdar Amitava
• Hendrix Greg S
• Nagendrakumar Anandhavel
• Patel Krunal
• Shenoy Kirthi
• Caraccio Danilo
• Lal Ankush
• Ross Frank F
• Gailey Adam D

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/4401

  for self repair · CPC title