Electron beam probing techniques and related structures

Patent metadata

Field	Value
Publication number	US-2024355685-A1
Application number	US-202418650718-A
Country	US
Kind code	A1
Filing date	Apr 30, 2024
Priority date	Dec 2, 2019
Publication date	Oct 24, 2024
Grant date	—

Abstract

Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

First claim

1 . (canceled)

2 . A method, comprising:
identifying a set of loops, wherein a first subset of the set of loops is coupled with a ground reference and a second subset of the set of loops is isolated from the ground reference; scanning the set of loops with an electron beam; generating an optical pattern based at least in part on scanning the set of loops with the electron beam; comparing the optical pattern to a second optical pattern; and determining a leakage path based at least in part on a difference between the optical pattern and the second optical pattern.

3 . The method of claim 2 , wherein generating the optical pattern comprises:
determining a brightness of each loop when scanned by the electron beam.

4 . The method of claim 2 , wherein the loops in the second subset are each configured to be electrically floating.

5 . The method of claim 2 , wherein the second optical pattern comprises one or more sets of loops having a first expected brightness, each set of loops having the first expected brightness adjacent to at least one loop having a second expected brightness that is lower than the first expected brightness.

6 . The method of claim 2 , wherein the loops are included in a top surface of a wafer when scanned with the electron beam.

7 . The method of claim 6 , wherein the wafer is located on a test stage, and wherein generating the optical pattern is based at least in part on a voltage potential of the test stage.

8 . The method of claim 6 , wherein scanning the set of loops with the electron beam comprises:
directing the electron beam to be incident upon one or more locations of the top surface of the wafer.

9 . The method of claim 2 , wherein the set of loops comprises at least one loop that is concentric about a second loop of the set of loops.

10 . A method, comprising:
identifying a set of loops, wherein a first subset of the set of loops is coupled with a ground reference and a second subset of the set of loops is isolated from the ground reference; generating an optical pattern by determining a brightness of each loop when scanned by an electron beam based at least in part on scanning the set of loops with the electron beam; comparing the optical pattern to a second optical pattern; and determining a leakage path based at least in part on a difference between the optical pattern and the second optical pattern.

11 . The method of claim 10 , wherein the loops in the second subset are each configured to be electrically floating.

12 . The method of claim 10 , wherein the second optical pattern comprises one or more sets of loops having a first expected brightness, each set of loops having the first expected brightness adjacent to at least one loop having a second expected brightness that is lower than the first expected brightness.

13 . The method of claim 10 , wherein the loops are included in a top surface of a wafer when scanned with the electron beam, and wherein the set of loops comprises at least one loop that is concentric about a second loop of the set of loops.

14 . The method of claim 13 , wherein the wafer is located on a test stage, and wherein generating the optical pattern is based at least in part on a voltage potential of the test stage.

15 . The method of claim 13 , wherein scanning the set of loops with the electron beam comprises:
directing the electron beam to be incident upon one or more locations of the top surface of the wafer.

16 . A method, comprising:
identifying a set of loops, wherein a first subset of the set of loops is coupled with a ground reference and a second subset of the set of loops are each configured to be electrically floating; generating an optical pattern based at least in part on scanning the set of loops with an electron beam; comparing the optical pattern to a second optical pattern; and determining a leakage path based at least in part on a difference between the optical pattern and the second optical pattern.

17 . The method of claim 16 , wherein generating the optical pattern comprises:
determining a brightness of each loop when scanned by the electron beam.

18 . The method of claim 16 , wherein the second optical pattern comprises one or more sets of loops having a first expected brightness, each set of loops having the first expected brightness adjacent to at least one loop having a second expected brightness that is lower than the first expected brightness.

19 . The method of claim 16 , wherein the loops are included in a top surface of a wafer when scanned with the electron beam, and wherein the set of loops comprises at least one loop that is concentric about a second loop of the set of loops.

20 . The method of claim 19 , wherein the wafer is located on a test stage, and wherein generating the optical pattern is based at least in part on a voltage potential of the test stage.

21 . The method of claim 19 , wherein scanning the set of loops with the electron beam comprises:
directing the electron beam to be incident upon one or more locations of the top surface of the wafer.

Assignees

• Micron Technology Inc

Inventors

• Majumdar Amitava
• Kotti Radhakrishna
• Rajashekharaiah Mallesh

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title