Method and memory system for writing data to dram submodules based on the data traffic demand

Patent metadata

Field	Value
Publication number	US-12013756-B2
Application number	US-202217894893-A
Country	US
Kind code	B2
Filing date	Aug 24, 2022
Priority date	Jan 24, 2022
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.

First claim

What is claimed is:

1. A memory system comprising:
a plurality of memory submodules, each submodule comprising:
a plurality of memory channels, each memory channel having a parity bit; and
a redundant array of independent devices (RAID) parity channel; and

a controller configured to:
receive a block of data for storage in the plurality of memory submodules;
determine whether a respective level of data traffic demand for a first memory submodule of the plurality of memory submodules is high or low based on a threshold value for current or recent memory demand and the threshold value comprising a percentage of a memory write request queue for the first memory submodule which is currently occupied with write requests;
wherein when the data traffic demand is low, (i) writing a portion of the block of data in the first memory submodule of the plurality of memory submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data; and
wherein when the data traffic demand is high, (i) only writing the portion of the block of data in the first memory submodule of the plurality of memory submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.

2. The memory system of claim 1 , wherein the determining is independent of the other submodules of the plurality of memory submodules.

3. The memory system of claim 1 , wherein the plurality of memory channels include dynamic random access memory (DRAM) channels coupled with a plurality of DRAM chips, each DRAM chip configured to store at least one of (i) a codeword including a set of data bytes and one or more parity bytes and (ii) a RAID byte.

4. The memory system of claim 1 , further comprising a lookup table (LUT) configured to store an indication that a parity data was updated during a prior write operation or was not updated during the prior write operation.

5. The memory system of claim 4 , wherein the LUT includes a table shared among the plurality of memory submodules.

6. The memory system of claim 4 , wherein the memory system is further configured to:
read the LUT to determine which parity bits are not set in the first memory submodule when the data traffic demand for the first memory submodule is low;
read the plurality of memory channels in the first memory submodule with the data associated with the unset parity bits upon determining which parity bits are not set;
calculate the parity bits and the raid parity byte for the data in the first memory submodule; and
write the calculated parity bits and the calculated RAID parity byte to the parity bits and RAID parity byte for the first memory submodule.

7. The memory system of claim 6 , wherein the controller is configured to calculate the parity bits and the RAID parity byte for the first memory submodule, the updated parity encompassing multiple prior write operations to the first memory submodule.

8. The memory system of claim 1 , further comprising:
a First-in-First-out (FIFO) outdated parity stack (OPS) configured to store an address of an outdated parity data, thereby indicating when the parity data was not updated during a prior write operation.

9. A method comprising:
receiving at a memory system a block of data for storage in a memory module of the memory system, the memory system comprising a plurality of memory submodules, each memory submodule including a plurality of memory channels, wherein each memory channel includes a parity bit;
determining via a controller of the memory system, whether a data traffic demand on a first memory submodule of the plurality of memory submodules is high or low based on a threshold value for current or recent memory demand wherein the threshold value comprises a percentage measure of a memory write request queue for the first memory submodule, the percentage indicating a degree to which the memory write request queue is currently occupied with write requests, the determining being independent of the other memory submodules of the plurality of submodules;
upon determining the data traffic demand is low, (i) writing at least a portion of the block of data in the first memory submodule, and (ii) concurrently updating a parity bit of the first memory submodule and updating a reductant array of independent devices (RAID) parity channel of the first memory submodule; and
upon determining the data traffic demand is high, (ii) only writing the data of the at least a portion of the block of data in the first memory submodule and (ii) deferring updating the parity bits and the RAID parity channel for the first memory submodule.

10. The method of claim 9 , wherein the method further comprises storing either a codeword comprising a set of data bytes and one or more parity bytes, or to storing a RAID byte, in dynamic random access memory (DRAM) channels coupled with a plurality of DRAM chips.

11. The method of claim 9 , further comprising storing in a lookup table (LUT) of the memory system an indication that a parity data was updated during a prior write operation or that the parity data was not updated during the prior write operation.

12. The method of claim 11 , further comprising storing the indication in an LUT which is a shared table for all of the plurality of memory submodules.

13. The method of claim 12 , further comprising:
subsequent to determining, monitoring the data traffic to identify when the data traffic demand for the first memory submodule is low;
upon determining that the data traffic demand for the first memory submodule is low, reading the LUT to determine which parity bits are not set in the first memory submodule;
upon determining which parity bits are not set, reading the plurality of memory channels in the first memory submodule with data associated with the unset parity bits;
calculating the parity bits and the raid parity byte for the data in the first memory submodule; and
writing the calculated parity bits and the calculated RAID parity byte to the parity bits and RAID parity byte for the first memory submodule.

14. The method of claim 13 , further comprising calculating, via the controller, the parity bits and the RAID parity byte for the first memory submodule to provide an updated parity encompassing multiple prior write operations at the first memory submodule.

15. The method of claim 9 , further comprising:
storing in a First-in-First-out (FIFO) outdated parity stack (OPS) of the memory system an address of outdated parity, and
upon sending an update parity command to the memory channels, retrieving the oldest address in the OPS FIFO and updating the corresponding parity.

16. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory system, causes the memory system to:
receive at a memory system a block of data for storage in a memory module of the memory system, the memory system comprising a plurality of memory submodules, each memory submodule including a plurality of memory channels, wherein each memory channel includes a parity bit;
determine via a controller of the memory system, whether a data traffic demand on a first memory submodule of the plurality of submodules is one of high or low based on a threshold value for current or recent memory demand wherein the threshold value comprises a percentage measure of a memory write request queue for the first memory submodule, the percentage indicating a degree to which the memory write request queue is currently occupied with write requests, the determining of the first memory sub

Assignees

• Micron Technology Inc

Inventors

• Yang Lingming
• Majumdar Amitava
• Thirumala Sandeep Krishna
• Gajera Nevil

Classifications

• G06F11/1096

  Parity calculation or recalculation after configuration or reconfiguration of the system · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title