Package substrate having porous dielectric layer
US-12593710-B2 · Mar 31, 2026 · US
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Williamson Jaimal Mallory patents
Williamson Jaimal Mallory is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Williamson Jaimal Mallory |
| Total patents | 32 |
| First publication | Mar 8, 2016 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Enhanced mold compound thermal conductivity
US-12489075-B2 · Dec 2, 2025 · US
Package substrate with cte matching barrier ring around microvias
US-2025323178-A1 · Oct 16, 2025 · US
Multilevel package substrate with stair shaped substrate traces
US-2025201689-A1 · Jun 19, 2025 · US
Semiconductor device package with improved die pad and solder mask design
US-12278205-B2 · Apr 15, 2025 · US
Multilevel package substrate with stair shaped substrate traces
US-12266597-B2 · Apr 1, 2025 · US
Package substrate with CTE matching barrier ring around microvias
US-12243835-B2 · Mar 4, 2025 · US
Package heat dissipation including a die attach film
US-12199008-B2 · Jan 14, 2025 · US
Package substrate having porous dielectric layer
US-2024282693-A1 · Aug 22, 2024 · US
Electronic device package emi shielding with grounded mold interconnect
US-2024178154-A1 · May 30, 2024 · US
Recent patents
Latest publications not already listed above.
Package substrate having porous dielectric layer
US-11973017-B2 · Apr 30, 2024 · US
Method of forming package substrate with partially recessed capacitor
US-11804382-B2 · Oct 31, 2023 · US
Multilevel package substrate with stair shaped substrate traces
US-2023207435-A1 · Jun 29, 2023 · US
Package substrate having porous dielectric layer
US-2023118218-A1 · Apr 20, 2023 · US
Package heat dissipation
US-2022319954-A1 · Oct 6, 2022 · US
Package substrate with cte matching barrier ring around microvias
US-2022254735-A1 · Aug 11, 2022 · US
Package substrate with partially recessed capacitor
US-2022223509-A1 · Jul 14, 2022 · US
Enhanced mold compound thermal conductivity
US-2022122936-A1 · Apr 21, 2022 · US
Package substrate with partially recessed capacitor
US-11289412-B2 · Mar 29, 2022 · US
Package substrate with CTE matching barrier ring around microvias
US-11270955-B2 · Mar 8, 2022 · US
Via integrity and board level reliability testing
US-11081406-B2 · Aug 3, 2021 · US
Package substrate with partially recessed capacitor
US-2020294899-A1 · Sep 17, 2020 · US
Semiconductor devices having metal posts for stress relief at flatness discontinuities
US-10748863-B2 · Aug 18, 2020 · US
Semiconductor device package with improved die pad and solder mask design
US-2020251436-A1 · Aug 6, 2020 · US
Package substrate with cte matching barrier ring around microvias
US-2020176396-A1 · Jun 4, 2020 · US
Leadframe having organic, polymerizable photo-imageable adhesion layer
US-10672692-B2 · Jun 2, 2020 · US
Via integrity and board level reliability testing
US-2019393106-A1 · Dec 26, 2019 · US
Semiconductor devices having metal posts for stress relief at flatness discontinuities
US-2018190606-A1 · Jul 5, 2018 · US
Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer
US-2018096860-A1 · Apr 5, 2018 · US
Process for forming leadframe having organic, polymerizable photo-imageable adhesion layer
US-2018096859-A1 · Apr 5, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Texas Instruments Inc | 32 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 23 |
| H01L24/16 | 20 |
| H10W90/701 | 20 |
| H10W70/685 | 20 |
| H01L23/49822 | 20 |