Semiconductor devices having metal posts for stress relief at flatness discontinuities

Patent metadata

Field	Value
Publication number	US-10748863-B2
Application number	US-201715835197-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Dec 30, 2016
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first body including a first surface;
a third body including a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body between the third surface and the fourth surface;
a second body contacting the first and the third surfaces; and
a closed structure, including a geometric plane shape, transecting the second body and directly contacting the edge, wherein a top and a bottom surface of the second body is coplanar with a top and a bottom surface of the closed structure respectively.

2. The device of claim 1 further comprising a bump contacting, and electrically connected to the third body and the closed structure.

3. The device of claim 2 , wherein the bump is attached to a portion of a lead frame.

4. The device of claim 2 , wherein the first body is on a semiconductor substrate.

5. The device of claim 4 further comprising a polymeric compound covering portions of the third body, second body, the bump and the semiconductor substrate.

6. The device of claim 1 , wherein:
the first body includes a first coefficient of thermal expansion (CTE);
the third body includes a third CTE;
the second body includes a second CTE higher than the first CTE and the third CTE; and
the closed structure includes a fourth CTE lower than the second CTE.

7. The device of claim 6 , wherein the first CTE is 16×10 −6 K −1 , the second CTE is 33×10 −6 K −1 , and the third CTE is 16×10 −6 K −1 .

8. The device of claim 1 , wherein the closed structure has top and bottom surfaces and sides forming a shape selected from a group consisting of a circle, hexagon, and a rectangle.

9. The device of claim 1 , wherein the closed structure includes a metal.

10. The device of claim 1 , wherein the edge includes a corner, or a peak.

11. The device of claim 1 , wherein the first body and the third body each comprise metal.

12. The device of claim 1 , wherein the second body includes a polymeric material.

13. The device of claim 1 , wherein the third body includes an under bump metal layer of copper or copper alloy.

14. A semiconductor device comprising:
a semiconductor substrate on a first body with a first surface;
a third body including a third surface contacting a portion of the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body between the third surface and the fourth surface;
a second body contacting the first and the third surfaces;
a closed structure, including a geometric plane shape, contacting the second body and contacting the edge, wherein a top and a bottom surface of the second body is coplanar with a top and a bottom surface of the closed structure respectively;
a bump contacting the third body;
a portion of a lead frame attached to the bump; and
a polymeric compound covering portions of the third body, second body, the bump, the portion of the lead frame, and the semiconductor substrate.

15. The device of claim 14 , wherein:
the first body includes a first coefficient of thermal expansion (CTE);
the third body includes a third CTE;
the second body includes a second CTE higher than the first CTE and the third CTE; and
the closed structure includes a fourth CTE lower than the second CTE.

16. The device of claim 15 , wherein the first CTE is 16×10 −6 K −1 , the second CTE is 33×10 −6 K −1 , and the third CTE is 16×10 −6 K −1 .

17. The device of claim 15 , wherein the closed structure transects the second body, and wherein the closed structure is within two parallel planes along two opposite surfaces of the second body.

18. The device of claim 14 , wherein the closed structure directly contacts the edge.

19. The device of claim 14 , wherein the closed structure includes a circular shape from a top view of the device, and wherein the closed structure includes copper or benzocyclobutene.

20. The device of claim 14 , wherein the first body and the third body each comprise metal.

21. The device of claim 14 , wherein the second body includes a polymeric material.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Li Guangxu

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title