Enhanced mold compound thermal conductivity

Patent metadata

Field	Value
Publication number	US-12489075-B2
Application number	US-202117219681-A
Country	US
Kind code	B2
Filing date	Mar 31, 2021
Priority date	Oct 20, 2020
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

In examples, a semiconductor package comprises a semiconductor die having a first surface on which circuitry is formed and a second surface opposite the first surface. The semiconductor package includes a mold compound, the second surface facing the mold compound. The mold compound covers the semiconductor die; a set of conductive vias exposed to a top surface of the mold compound and coupled to a metal layer in the package; a set of first conductive members vertically aligned with the semiconductor die and exposed to the top surface of the mold compound; and a set of second conductive members coupling at least some of the set of conductive vias to at least some of the set of first conductive members. The set of second conductive members is exposed to the top surface of the mold compound.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a semiconductor die having a first surface on which circuitry is formed and a second surface opposite the first surface; and a mold compound, the second surface facing the mold compound, the mold compound physically contacting:
the semiconductor die;
a set of conductive vias exposed to a top surface of the semiconductor package and coupled to a metal layer in the package;
a set of first conductive members vertically aligned with the semiconductor die and exposed to the top surface of the semiconductor package; and
a set of second conductive members coupling at least some of the set of conductive vias to at least some of the set of first conductive members, the set of second conductive members exposed to the top surface of the semiconductor package.

2 . The package of claim 1 , wherein each of the set of conductive vias has a diameter ranging from 0.55 mm to 0.7 mm, and wherein each of the set of first conductive members has a diameter ranging from 0.55 mm to 0.7 mm.

3 . The package of claim 1 , wherein the set of conductive vias and the set of first conductive members extend vertically, and wherein the set of second conductive members extend horizontally.

4 . The package of claim 1 , wherein at least one of the set of conductive vias includes a first segment having an approximately uniform horizontal cross-sectional diameter and a second segment having a progressively enlarging horizontal cross-sectional diameter, the second segment positioned closer to the top surface of the semiconductor package than the first segment.

5 . The package of claim 1 , further comprising a solder mask in a substrate of the package, the solder mask including a solder mask orifice, the metal layer positioned in the solder mask orifice.

6 . A semiconductor package, comprising:
a substrate including a metal layer and a solder mask abutting the metal layer, the solder mask abutting a first conductive via coupled to the metal layer; a semiconductor die having a first surface on which circuitry is formed and a second surface opposite the first surface, the first surface facing the metal layer and coupled to the metal layer; and a mold compound covering the solder mask and the semiconductor die, the mold compound physically contacting:
a second conductive via coupled to the first conductive via, the second conductive via exposed to a top surface of the semiconductor package;
a first conductive member vertically aligned with the semiconductor die and facing the second surface of the semiconductor die, the first conductive member exposed to the top surface of the semiconductor package; and
a second conductive member coupling the second conductive via to the first conductive member.

7 . The semiconductor package of claim 6 , wherein the semiconductor package is a flip-chip chip scale package (FCCSP).

8 . The semiconductor package of claim 6 , wherein at least some of the mold compound is positioned between the first conductive member and the second surface of the semiconductor die.

9 . The semiconductor package of claim 6 , wherein the second conductive via includes a first segment having an approximately uniform horizontal cross-sectional diameter and a second segment having a progressively enlarging horizontal cross-sectional diameter, the second segment positioned closer to the top surface of the semiconductor package than the first segment.

10 . The semiconductor package of claim 6 , wherein a pitch between the second conductive via and a third conductive via most proximate to the second conductive via ranges from 0.5 mm to 0.8 mm.

11 . The semiconductor package of claim 10 , wherein the second conductive via has a cross-sectional diameter ranging from 0.55 mm to 0.7 mm.

12 . A semiconductor package, comprising:
a substrate including a metal layer and a solder mask, the solder mask including a solder mask orifice within which the metal layer is positioned; a first conductive member coupled to the metal layer; a semiconductor die having a first surface on which circuitry is formed and a second surface opposite the first surface, the first surface facing the metal layer and coupled to the metal layer; a mold compound covering the solder mask and the semiconductor die, the mold compound physically contacting:
a conductive via coupled to the first conductive member; and
a second conductive member vertically aligned with the semiconductor die, the second surface of the semiconductor die facing the second conductive member.

13 . The semiconductor package of claim 12 , wherein the first conductive member is positioned in the solder mask orifice.

14 . The semiconductor package of claim 13 , wherein the first conductive member does not contact the solder mask.

15 . The semiconductor package of claim 12 , further comprising a third conductive member coupling the conductive via to the second conductive member.

16 . The semiconductor package of claim 15 , wherein the third conductive member is exposed to a top surface of the mold compound.

17 . The semiconductor package of claim 12 , wherein the conductive via and the second conductive member are exposed to a top surface of the mold compound.

18 . The semiconductor package of claim 12 , wherein the first conductive member is composed of a metallic paste.

19 . The semiconductor package of claim 12 , wherein the conductive via includes a first segment having an approximately uniform cross-sectional diameter and a second segment having a progressively enlarging cross-sectional diameter, the second segment positioned closer to a top surface of the mold compound than the first segment.

20 . The semiconductor package of claim 12 , wherein at least some of the mold compound is positioned between the second conductive member and the second surface of the semiconductor die.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Nguyen Hiep Xuan

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title