Multilevel package substrate with stair shaped substrate traces

Patent metadata

Field	Value
Publication number	US-2025201689-A1
Application number	US-202519069984-A
Country	US
Kind code	A1
Filing date	Mar 4, 2025
Priority date	Dec 28, 2021
Publication date	Jun 19, 2025
Grant date	—

Abstract

An electronic device includes a multilevel package substrate with first and second levels, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, and the first level including a second trace layer with a stair shaped second conductive trace feature, the second conductive trace feature having a first portion with a first thickness, and a second portion, having a second thickness greater than the first thickness.

First claim

What is claimed is:

1 . An electronic device, comprising:
a multilevel package substrate having a first level and a second level, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, the first level on the second level and including a second trace layer with a second conductive trace feature, the second conductive trace feature having a first portion and a second portion, the first portion having a first thickness, the second portion having a second thickness, wherein the second thickness is greater than the first thickness; and a die electrically coupled to the multilevel package substrate, wherein the second portion of the second conductive trace feature locates within selective areas of the first level and the selective areas are along a periphery of the die.

2 . The electronic device of claim 1 , wherein:
the multilevel package substrate includes a core dielectric layer, a third level, and a fourth level; the core dielectric layer has opposite first and second sides; the second level on the first side of the core dielectric layer; the third level on the second side of the core dielectric layer, the third level including a third trace layer with a third conductive trace feature, a conductive second via that contacts the third conductive trace feature, and a second dielectric layer; the fourth level on the third level, the fourth level including a fourth trace layer with a fourth conductive trace feature; and a solder ball attached to the fourth conductive trace feature.

3 . The electronic device of claim 2 , wherein the fourth conductive trace feature has a first portion and a second portion, the first portion of the fourth conductive trace feature having a third thickness, the second portion of the fourth conductive trace feature having a fourth thickness, and the fourth thickness greater than the third thickness.

4 . The electronic device of claim 3 , wherein:
the first thickness is 10 to 20 μm; the second thickness is 5 to 15 μm greater than the first thickness; the third thickness is 10 to 20 μm; and the fourth thickness is 5 to 15 μm greater than the third thickness.

5 . The electronic device of claim 1 , wherein:
the selective areas of the first level comprise a first region of the first level proximate a lateral side of the die.

6 . The electronic device of claim 5 , wherein the first region of the first level is under the die.

7 . The electronic device of claim 3 , wherein:
the first level includes multiple second conductive trace features, each having respective first and second portions, the respective first portions having the first thickness, and the respective second portions having the second thickness; and the fourth level includes multiple fourth conductive trace features, each having respective first and second portions, the respective first portions of the fourth conductive trace features having the third thickness, and the respective second portions of the fourth conductive trace features having the fourth thickness.

8 . The electronic device of claim 1 , wherein:
the first thickness is 10 to 20 μm; and the second thickness is 5 to 15 μm greater than the first thickness.

9 . The electronic device of claim 1 , wherein the first level includes multiple second conductive trace features, each having respective first and second portions, the respective first portions having the first thickness, and the respective second portions having the second thickness.

10 . A multilevel package substrate, comprising:
a first level; and a second level; the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer; and the first level on the second level and including a second trace layer with a second conductive trace feature, the second conductive trace feature having a first portion and a second portion, the first portion having a first thickness, the second portion having a second thickness, wherein the second thickness is greater than the first thickness, and wherein the second portion of the second conductive trace feature locates within selective areas of the first level and the selective areas are along a periphery of a die attached to the multilevel package substrate.

11 . The multilevel package substrate of claim 10 , further comprising a core dielectric layer, a third level, and a fourth level; wherein:
the core dielectric layer has opposite first and second sides; the second level on the first side of the core dielectric layer; the third level on the second side of the core dielectric layer, the third level including a third trace layer with a third conductive trace feature, a conductive second via that contacts the third conductive trace feature, and a second dielectric layer; the fourth level on the third level, the fourth level including a fourth trace layer with a fourth conductive trace feature; and a solder ball attached to the fourth conductive trace feature.

12 . The multilevel package substrate of claim 11 , wherein the fourth conductive trace feature has a first portion and a second portion, the first portion of the fourth conductive trace feature having a third thickness, the second portion of the fourth conductive trace feature having a fourth thickness, and the fourth thickness greater than the third thickness.

13 . The multilevel package substrate of claim 12 , wherein:
the first thickness is 10 to 20 μm; the second thickness is 5 to 15 μm greater than the first thickness; the third thickness is 10 to 20 μm; and the fourth thickness is 5 to 15 μm greater than the third thickness.

14 . The multilevel package substrate of claim 10 , wherein:
the selective areas of the first level comprise a first region of the first level proximate a lateral side of the die.

15 . The multilevel package substrate of claim 14 , wherein the first region of the first level is under the die.

16 . The multilevel package substrate of claim 10 , wherein:
the first thickness is 10 to 20 μm; and the second thickness is 5 to 15 μm greater than the first thickness.

17 . A method, comprising:
forming a second level on a side of a core dielectric layer, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer; and forming a first level on the second level, the first level including a second trace layer with a second conductive trace feature, the second conductive trace feature having a first portion and a second portion, the first portion having a first thickness, the second portion having a second thickness, and the second thickness greater than the first thickness, wherein the second portion of the second conductive trace feature locates within selective areas of the first level and the selective areas are along a periphery of a die attached to the first level.

18 . The method of claim 17 , further comprising:
forming a third level on a second side of the core dielectric layer, the third level including a third trace layer with a third conductive trace feature, a conductive second via that contacts the third conductive trace feature, and a second dielectric layer; and forming a fourth level on the third level, the fourth level including a fourth trace layer with a fourth conductive tr

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Lo Chun Ping
• Suzuki Yutaka

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title