Package substrate with cte matching barrier ring around microvias

Patent metadata

Field	Value
Publication number	US-2025323178-A1
Application number	US-202519068631-A
Country	US
Kind code	A1
Filing date	Mar 3, 2025
Priority date	Nov 30, 2018
Publication date	Oct 16, 2025
Grant date	—

Abstract

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

First claim

1 . A method of fabricating a package substrate, comprising:
forming a pattern of a first photosensitive material on a core metal layer to form a first and a second dielectric aperture; plating a first metal layer into the first dielectric aperture and the second dielectric aperture on the core metal layer to partially fill the first and second dielectric apertures; removing the first photosensitive material to reveal at least one framed via hole including a raised ring of the first metal layer that is around the via hole; plating a second metal layer on the first metal layer and in the via hole, where the second metal layer has a smaller outer dimension throughout its thickness as compared to outer dimension of the first metal layer throughout its thickness, and forming a dielectric layer that surrounds the first metal layer and the second metal layer, wherein a top surface of the dielectric layer is planar with respect to a top surface of the second metal layer to provide a build-up layer with a planarized surface having a filled via hole.

2 . The method of claim 1 , further comprising:
before the plating of the second metal layer forming a pattern of a second photosensitive material with a pattern opening having a tapered shape over the framed via hole, and after the plating of the second metal layer removing the second photosensitive material, wherein the forming the dielectric layer comprises forming a dielectric laminate layer.

3 . The method of claim 1 ,
wherein the forming of the dielectric layer is before the plating of the second metal layer, and wherein the forming of the dielectric layer comprises forming a second photosensitive dielectric material with an aperture to provide the pattern opening having the tapered shape over the framed via hole.

4 . The method of claim 1 ,
wherein the forming of the dielectric layer is before the plating of the second metal layer, and wherein the forming of the dielectric layer comprises forming a dielectric laminate layer, further comprising laser drilling an aperture in the dielectric laminate layer to provide the pattern opening having the tapered shape over the framed via hole.

5 . The method of claim 1 , wherein the first metal layer and the second metal layer both comprise a same metal material and the raised ring has a coefficient of thermal expansion (CTE) matching material that is within 5 ppm/° C. of a CTE of the same metal material.

6 . The method of claim 1 , further comprising forming a metal build-up layer on the planarized surface, and then repeating the method to form at least one more of the build-up layer.

7 . The method of claim 1 , further comprising attaching at least one integrated circuit (IC) die with bump features to the build-up layer to provide coupling to the filled via hole, wherein the raised ring is positioned within 10 millimeters of under an outer edge of the IC die.

8 . The method of claim 7 , wherein the raised ring is positioned including under the outer edge of the IC die.

9 . The method of claim 7 , further comprising attaching the package substrate opposite to the IC die with bump features to a printed circuit board (PCB).

10 . A method of fabricating a packaged integrated circuit (IC) device, comprising:
providing at least one IC die, and providing a package substrate comprising:
forming a pattern of a first photosensitive material on a core metal layer to form a first and a second dielectric aperture;
plating a first metal layer into the first dielectric aperture and the second dielectric aperture on the core metal layer to partially fill the first and second dielectric apertures;
removing the first photosensitive material to reveal at least one framed via hole including a raised ring of the first metal layer that is around the via hole;
plating a second metal layer on the first metal layer and in the via hole, where the second metal layer has a smaller outer dimension throughout its thickness as compared to outer dimension of the first metal layer throughout its thickness;
forming a dielectric layer that surrounds the first metal layer and the second metal layer, wherein a top surface of the dielectric layer is planar with respect to a top surface of the second metal layer to provide a build-up layer with a planarized surface having a filled via hole; and
attaching the at least one IC die to the substrate.

11 . The method of claim 10 , further comprising:
before the plating of the second metal layer forming a pattern of a second photosensitive material with a pattern opening having a tapered shape over the framed via hole, and after the plating of the second metal layer removing the second photosensitive material, wherein the forming the dielectric layer comprises forming a dielectric laminate layer.

12 . The method of claim 10 ,
wherein the forming of the dielectric layer is before the plating of the second metal layer, and wherein the forming of the dielectric layer comprises forming a second photosensitive dielectric material with an aperture to provide the pattern opening having the tapered shape over the framed via hole.

13 . The method of claim 10 ,
wherein the forming of the dielectric layer is before the plating of the second metal layer, and wherein the forming of the dielectric layer comprises forming a dielectric laminate layer, further comprising laser drilling an aperture in the dielectric laminate layer to provide the pattern opening having the tapered shape over the framed via hole.

14 . The method of claim 10 , wherein the first metal layer and the second metal layer both comprise a same metal material and the raised ring has a coefficient of thermal expansion (CTE) matching material that is within 5 ppm/° C. of a CTE of the same metal material.

15 . The method of claim 10 , further comprising forming a metal build-up layer on the planarized surface, and then repeating the method to form at least one more of the build-up layer.

16 . The method of claim 10 , wherein the at least one IC device includes bump features is attached to the build-up layer to provide coupling to the filled via hole, wherein the raised ring is positioned within 10 millimeters of under an outer edge of the IC die.

17 . The method of claim 16 , wherein the raised ring is positioned including under the outer edge of the IC die.

18 . The method of claim 16 , further comprising attaching the package substrate opposite to the IC die with bump features to a printed circuit board (PCB).

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Li Guangxu

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title