Package heat dissipation

Patent metadata

Field	Value
Publication number	US-2022319954-A1
Application number	US-202117219602-A
Country	US
Kind code	A1
Filing date	Mar 31, 2021
Priority date	Mar 31, 2021
Publication date	Oct 6, 2022
Grant date	—

Abstract

In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; a semiconductor die having first and second opposing surfaces, the first surface coupled to the conductive pillar; a die attach film abutting the second surface of the semiconductor die; a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film, the metal layer surface exposed to an exterior of the package; and a mold compound layer covering the substrate.

2 . The package of claim 1 , wherein the die attach film includes a 2:1 ratio of resin to a diamine curing agent.

3 . The package of claim 2 , wherein the resin includes a 7:4 ratio of diglycidyl ether of bisphenol F to phenoxy resin; a greater than 80 wt. % silver particles or flake; approximately 0.5 wt. % of 1-cyanoethyl-2-ethyl-4-methylmidazole; and approximately 2 wt. % 3-glycidoxypropyl trimethoxysilane

4 . The package of claim 1 , wherein the metal layer includes a copper layer.

5 . The package of claim 1 , wherein the metal layer includes a copper layer and a plating layer.

6 . The package of claim 1 , wherein the mold compound layer includes a mold compound layer surface facing away from the substrate, the mold compound layer surface approximately co-planar with the metal layer surface.

7 . A semiconductor package, comprising:
a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; a semiconductor die having first and second opposing surfaces, the first surface coupled to the conductive pillar; a die attach film abutting the second surface of the semiconductor die and having a die attach film surface facing away from the semiconductor die; and a mold compound layer covering the substrate and including a mold compound layer surface facing away from the substrate, the mold compound layer surface approximately co-planar with the die attach film surface.

8 . The package of claim 7 , wherein the die attach film has a thermal conductivity of at least 3 watts per meter-Kelvin.

9 . The package of claim 7 , wherein a thickness of the die attach film ranges between 5 microns and 100 microns.

10 . The package of claim 7 , wherein the die attach film includes a 2:1 ratio of resin to a diamine curing agent.

11 . A system, comprising:
a printed circuit board (PCB); and a flip-chip chip scale package (FCCSP) coupled to the PCB by way of a solder ball, the FCCSP including:
a first conductive layer coupled to the solder ball;
a second conductive layer coupled to the first conductive layer;
a conductive pillar coupled to the second conductive layer;
a semiconductor die having first and second surfaces, the first surface of the semiconductor die coupled to the conductive pillar, the second surface of the semiconductor die facing away from the conductive pillar; and
a polymerized and cured thermally conductive paste abutting the second surface of the semiconductor die and having a surface facing away from the semiconductor die,
wherein a roughness of the surface of the thermally conductive paste is based on a pressure with which the thermally conductive paste is applied to the second surface of the semiconductor die.

12 . The system of claim 11 , wherein the thermally conductive paste includes a 2:1 ratio of diglycidyl ether of bisphenol F to diamine curing agent; greater than 80 wt. % silver particles or flake; 0.5 wt. % of 1-cyanoethyl-2-ethyl-4-methylimidazole; and 2 wt. % of 3-glycidoxypropyl trimethoxysilane.

13 . The system of claim 12 , wherein the thermally conductive paste has a thickness ranging from 25 to 200 microns.

14 . The system of claim 11 , further comprising a mold compound layer abutting a second surface of the thermally conductive paste.

15 . The system of claim 14 , wherein the surface of the thermally conductive paste is approximately co-planar with a surface of the mold compound layer, the surface of the mold compound layer exposed to an exterior of the FCCSP.

16 . The system of claim 11 , wherein the roughness of the surface of the thermally conductive paste is based on a volume of a cavity in which the thermally conductive paste is positioned.

17 . The system of claim 11 , wherein the surface of the thermally conductive paste is exposed to an exterior of the FCCSP.

18 . The system of claim 11 , further comprising a metal layer abutting the surface of the thermally conductive paste.

19 . The system of claim 18 , further comprising a passivation layer abutting the copper layer.

20 . The system of claim 18 , further comprising a nickel palladium gold plating layer abutting the copper layer.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Zhang Rongwei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117 Primary

  the substrate having spherical bumps for external connection · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title