Package substrate with CTE matching barrier ring around microvias

Patent metadata

Field	Value
Publication number	US-12243835-B2
Application number	US-202217679082-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Nov 30, 2018
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

First claim

The invention claimed is:

1. A method of fabricating a multi-layer package substrate, comprising:
forming a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching at least one integrated circuit (IC) die;
wherein the first build-up layer includes a first tapered microvia extending through the first dielectric layer and the second build-up layer includes at least a second tapered microvia extending through the second dielectric layer that is coupled to the first microvia;
further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a metal of the second tapered microvia positioned along only a portion of a height of at least the second tapered microvia along a smallest diameter of the second tapered microvia, the barrier ring directly connected to the metal of the second tapered microvia.

2. The method of claim 1 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

3. The method of claim 1 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

4. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

5. The method of claim 1 , wherein the barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

6. The method of claim 1 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

7. The method of claim 1 , further providing a core that the first and second build-up layers are on.

8. A method of fabricating a packaged integrated circuit (IC) device, comprising:
providing at least one IC die, and
providing a package substrate comprising:
a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching the IC die;
wherein the first build-up layer includes a first tapered microvia extending through the first dielectric layer and the second build-up layer includes at least a second tapered microvia extending through the second dielectric layer that is coupled to the first tapered microvia;
further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second tapered microvia positioned along only a portion of a height of at least the second tapered microvia along a smallest diameter of the second tapered microvia, the barrier ring directly connected to the metal of the second tapered microvia.

9. The method of claim 8 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

10. The method of claim 8 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

11. The method of claim 8 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

12. The method of claim 10 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

13. The method of claim 9 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

14. The method of claim 9 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

15. The method of claim 10 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

16. The method of claim 8 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

17. The method of claim 8 , wherein the barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

18. The method of claim 8 , further comprising a core that the first and second build-up layers are on.

19. The method of claim 7 , wherein the core comprises organic material.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Li Guangxu

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title