Via integrity and board level reliability testing

Patent metadata

Field	Value
Publication number	US-11081406-B2
Application number	US-201816015965-A
Country	US
Kind code	B2
Filing date	Jun 22, 2018
Priority date	Jun 22, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

Described examples provide a method to evaluate reliability of ball grid array products in which an interconnect stress test is performed that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board, and the reliability of ball grid array products manufactured using package substrate portions of the production panel is evaluated according to the results of the interconnect stress test. A test coupon includes a rigid core material layer, dielectric layers laminated between copper layers above and below the core material layer, conductive micro-vias that extend through at least one of the dielectric layers between two of the copper layers, and conductive land pads on an outer one of the dielectric layers, the conductive land pads individually contacting one of the micro-vias.

First claim

What is claimed is:

1. A method, comprising:
manufacturing a production panel that includes:
a test coupon portion with a plurality of land pads connected to outer layer micro-vias on a first side of the test coupon portion, and
a plurality of package substrate portions;

separating the test coupon portion and the plurality of package substrate portions from the production panel;
attaching a printed circuit board to the test coupon portion using a surface mount process to solder at least some of the land pads of the test coupon portion to conductive features of the printed circuit board; and
performing an interconnect stress test that passes current through the outer layer micro-vias of the test coupon portion.

2. The method of claim 1 ,
wherein the production panel includes a first test coupon portion, and a second test coupon portion;
wherein separating the test coupon portion from the production panel includes:
separating the first test coupon portion from the production panel, and
separating the second test coupon portion from the production panel;

wherein attaching a printed circuit board to the test coupon portion includes:
attaching a first printed circuit board to the first test coupon portion using a first surface mount process to solder land pads of the first test coupon portion to conductive features of the first printed circuit board, and
attaching a second printed circuit board to the second test coupon portion using a second surface mount process to solder land pads of the second test coupon portion to conductive features of the second printed circuit board.

3. The method of claim 2 , wherein the first surface mount process uses a first ball solder metallurgy to solder the land pads of the first test coupon portion to the conductive features of the first printed circuit board; and wherein the second surface mount process uses a different second ball solder metallurgy to solder the land pads of the second test coupon portion to the conductive features of the second printed circuit board.

4. The method of claim 3 , further comprising:
evaluating the first and second ball solder metallurgies according to results of the interconnect stress test.

5. The method of claim 2 , further comprising:
manufacturing a plurality of ball grid array (BGA) products using the package substrate portions;
evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

6. The method of claim 2 , further comprising:
manufacturing a plurality of ball grid array (BGA) products using the package substrate portions;
evaluating solder joint reliability of the BGA products according to results of the interconnect stress test.

7. The method of claim 1 , further comprising:
manufacturing a plurality of ball grid array (BGA) products using the package substrate portions;
evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

8. The method of claim 7 , further comprising:
evaluating solder joint reliability of the BGA products according to results of the interconnect stress test.

9. The method of claim 1 , further comprising:
manufacturing a plurality of ball grid array (BGA) products using the package substrate portions;
evaluating solder joint reliability of the BGA products according to results of the interconnect stress test.

10. The method of claim 1 , further comprising:
evaluating a ball solder metallurgy according to results of the interconnect stress test.

11. The method of claim 1 , further comprising:
attaching a second printed circuit board to the test coupon portion using a second surface mount process to solder at least some further land pads of the test coupon portion to conductive features of the second printed circuit board; and
performing the interconnect stress test that passes current through further outer layer micro-vias of the test coupon portion.

12. A method, comprising:
performing an interconnect stress test that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board;
evaluating reliability of BGA products manufactured using package substrate portions of the production panel according to results of the interconnect stress test.

13. The method of claim 12 , wherein evaluating the reliability of the BGA products comprises evaluating solder joint reliability of the BGA products according to the results of the interconnect stress test.

14. The method of claim 13 , wherein evaluating the solder joint reliability of the BGA products comprises evaluating a ball solder metallurgy according to the results of the interconnect stress test.

15. The method of claim 13 , wherein evaluating the reliability of the BGA products comprises evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

16. The method of claim 12 , wherein evaluating the reliability of the BGA products comprises evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

17. The method of claim 12 , further comprising:
soldering a second printed circuit board to the test coupon portion before performing the interconnect stress test.

18. A method, comprising:
separating a test coupon portion and a plurality of package substrate portions from a production panel, the test coupon portion including a plurality of land pads connected to outer layer micro-vias;
soldering the land pads of the test coupon portion to conductive features of a printed circuit board;
performing an interconnect stress test that passes current through the outer layer micro-vias of the test coupon portion; and
evaluating reliability of BGA products made from the package substrate portions according to results of the interconnect stress test.

19. The method of claim 18 , wherein evaluating the reliability of the BGA products comprises evaluating solder joint reliability of the BGA products according to the results of the interconnect stress test.

20. The method of claim 19 , wherein evaluating the evaluating the solder joint reliability of the BGA products comprises evaluating a ball solder metallurgy according to the results of the interconnect stress test.

21. The method of claim 19 , wherein evaluating the reliability of the BGA products comprises evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

22. The method of claim 18 , wherein evaluating the reliability of the BGA products comprises evaluating micro-via reliability of the BGA products according to results of the interconnect stress test.

23. The method of claim 18 , further comprising:
soldering further land pads of the test coupon portion to conductive features of a second printed circuit board before performing the interconnect stress test.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Davis Ethan Tilden

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title