Package substrate with CTE matching barrier ring around microvias

Patent metadata

Field	Value
Publication number	US-11270955-B2
Application number	US-201816205436-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Nov 30, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

First claim

The invention claimed is:

1. A multi-layer package substrate, comprising:
a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching at least one integrated circuit (IC) die;
wherein the first build-up layer includes a first tapered microvia extending through the first dielectric layer and the second build-up layer includes at least a second tapered microvia extending through the second dielectric layer that is coupled to the first microvia;
further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a metal of the second tapered microvia positioned along only a portion of a height of at least the second tapered microvia along a smallest diameter of the second tapered microvia, the barrier ring directly connected to the metal of the second tapered microvia.

2. The multi-layer package substrate of claim 1 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

3. The multi-layer package substrate of claim 1 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

4. The multi-layer package substrate of claim 1 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

5. The multi-layer package substrate of claim 1 , wherein the barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

6. The multi-layer package substrate of claim 1 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

7. The multi-layer package substrate of claim 1 , further comprising a core that the first and second build-up layers are on.

8. The multi-layer package substrate of claim 1 , wherein the barrier ring does not extend outside the second build-up layer.

9. The multi-layer package substrate of claim 1 , further including another barrier ring within the first build-up layer that does not extend outside the first build-up layer.

10. A packaged integrated circuit (IC) device, comprising:
at least one IC die, and
a package substrate comprising:
a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching the IC die;
wherein the first build-up layer includes a first tapered microvia extending through the first dielectric layer and the second build-up layer includes at least a second tapered microvia extending through the second dielectric layer that is coupled to the first tapered microvia;
further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second tapered microvia positioned along only a portion of a height of at least the second tapered microvia along a smallest diameter of the second tapered microvia, the barrier ring directly connected to the metal of the second tapered microvia.

11. The packaged IC device of claim 10 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

12. The packaged IC device of claim 11 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

13. The packaged IC device of claim 11 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

14. The packaged IC device of claim 10 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second tapered microvia.

15. The packaged IC device of claim 14 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second tapered microvia.

16. The packaged IC device of claim 14 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

17. The packaged IC device of claim 10 , wherein the CTE matching material and the second tapered microvia both comprise a same material.

18. The packaged IC device of claim 10 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

19. The packaged IC device of claim 10 , wherein the barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

20. The packaged IC device of claim 10 , further comprising a core that the first and second build-up layers are on.

21. The packaged IC device of claim 20 , further including another barrier ring within the first build-up layer that does not extend outside the first build-up layer.

22. The packaged IC device of claim 20 , wherein the core comprises organic material.

23. The packaged IC device of claim 10 , wherein the barrier ring does not extend outside the second build-up layer.

24. The packaged IC device of claim 10 , further including another barrier ring within the first build-up layer that does not extend outside the first build-up layer.

25. A packaged integrated circuit (IC) device, comprising:
at least one IC die, and
a package substrate comprising:
a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching the IC die;
wherein the first build-up layer includes a first microvia extending through the first dielectric layer and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia;
further comprising a metal barrier ring positioned along and electrically connected to only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

26. The packaged IC device of claim 25 , wherein a coefficient of thermal expansion (CTE) of the metal barrier ring has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second microvia.

27. The packaged IC device of claim 26 , wherein the metal barrier ring and the second microvia both comprise a same material.

28. The packaged IC device of claim 25 , wherein the metal barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second microvia.

29. The packaged IC device of claim 25 , wherein the metal barrier ring and the second microvia both comprise a same material.

30. The packaged IC device of claim 25 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

31. The packaged IC device of claim 25 , wherein the metal barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

32. The packaged IC device of claim 25 , further comprising a core that th

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Li Guangxu

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title