Package substrate with cte matching barrier ring around microvias

Patent metadata

Field	Value
Publication number	US-2020176396-A1
Application number	US-201816205436-A
Country	US
Kind code	A1
Filing date	Nov 30, 2018
Priority date	Nov 30, 2018
Publication date	Jun 4, 2020
Grant date	—

Abstract

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

First claim

1 - 9 . (canceled)

10 . A multi-layer package substrate, comprising:
a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching at least one integrated circuit (IC) die; wherein the first build-up layer includes a first microvia extending through the first dielectric layer and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia; further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia,

11 . The multi-layer package substrate of claim 10 , wherein the CTE matching material has a CTE that is within 5 ppm/° C of a CTE of the metal of the second microvia.

12 . The multi-layer package substrate of claim 10 , wherein the CTE matching material and the second microvia both comprise a same material.

13 . The multi-layer package substrate of claim 10 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

14 . The multi-layer package substrate of claim 10 , wherein the harrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

15 . The multi-layer package substrate of claim 10 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second microvia.

16 . The multi-layer package substrate of claim 10 , further comprising a core that the first and second build-up layers are on.

17 . A packaged integrated circuit (IC) device, comprising:
at least one IC die, and a package substrate comprising: a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching the IC die; wherein the first build-up layer includes a first microvia extending through the first dielectric layer and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia; further comprising a barrier ring having a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

18 . The packaged IC device of claim 17 , wherein the CTE matching material has a CIE that is within 5 ppm/° C. of a CTE of the metal of the second microvia.

19 . The packaged IC device of claim 17 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second microvia.

20 . The packaged IC device of claim 17 , wherein the CTE matching material and the second microvia both comprise a same material,

21 . The packaged IC device of claim 19 , wherein the CTE matching material has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second microvia.

22 . The packaged IC device of claim 18 , wherein the barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second microvia.

23 . The packaged IC device of claim 18 , wherein the CTE matching material and the second microvia both comprise a same material,

24 . The packaged IC device of claim 19 , wherein the CTE matching material and the second microvia both comprise a same material.

25 . The packaged IC device of claim 17 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

26 . The packaged IC device of claim 17 , wherein the barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

27 . The packaged IC device of claim 17 , further comprising a core that the first and second build-up layers are on.

28 . The packaged IC device of claim 27 , wherein the core comprises organic material.

29 . A packaged integrated circuit (IC) device, comprising:
at least one IC die, and a package substrate comprising: a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer, wherein the second build-up layer includes a top metal surface that is configured for attaching the IC die; wherein the first build-up layer includes a first microvia extending through the first dielectric layer and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia; further comprising a metal barrier ring positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

30 . The packaged IC device of claim 29 , wherein a coefficient of thermal expansion (CTE) of the metal barrier ring has a CTE that is within 5 ppm/° C. of a CTE of the metal of the second microvia.

31 . The packaged IC device of claim 29 , wherein the metal barrier ring is 2 μm to 8 μm thick and has an outer diameter that is at least 10% greater than an outer diameter of the second microvia,

32 . The packaged IC device of claim 29 , wherein the metal barrier ring and the second microvia both comprise a same material.

33 . The packaged IC device of claim 30 , wherein the metal barrier ring and the second microvia both comprise a same material.

34 . The packaged IC device of claim 29 , wherein the first dielectric layer and the second dielectric layer both comprise an organic dielectric polymer.

35 . The packaged IC device of claim 29 , wherein the metal barrier ring is positioned within 10 millimeters under at least one outer edge of the IC die.

36 . The packaged IC device of claim 29 , further comprising a core that the first and second build-up layers are on.

37 . The packaged IC device of claim 36 , wherein the core comprises organic material.

38 . The multi-layer package substrate of claim 10 , wherein the barrier ring does not extend outside the second build-up layer.

39 . The multi-layer package substrate of claim 10 , further including another barrier ring within the first build-up layer that does not extend outside the first build-up layer.

40 . The packaged IC device of claim 17 , wherein the barrier ring does not extend outside the second build-up layer,

41 . The packaged IC device of claim 17 , further including another barrier ring within the first build-up layer that does not extend outside the first build-up layer.

42 . The packaged IC device of claim 29 , wherein the barrier ring does not extend outside the second build-up layer.

43 . The packaged IC device of claim 27 , further including another barrier ring within the f

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Li Guangxu

Classifications

• H01L23/49822

  Electricity · mapped topic

• H01L21/4857

  Electricity · mapped topic

• H01L23/562 Primary

  Electricity · mapped topic

• H01L21/486

  Electricity · mapped topic

• H01L23/49827

  Electricity · mapped topic