Method of forming package substrate with partially recessed capacitor

Patent metadata

Field	Value
Publication number	US-11804382-B2
Application number	US-202217707872-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Mar 13, 2019
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

First claim

What is claimed is:

1. A method of forming a semiconductor package comprising:
mounting a semiconductor die on a multilayer substrate to electrically connect the semiconductor die to a first set of electrical contacts of the multilayer substrate,
wherein the multilayer substrate comprises:
a dielectric layer;
a first conductive layer forming the first set of electrical contacts on a first side of the dielectric layer;
a second conductive layer forming a second set of electrical contacts on a second side of the dielectric layer, the second set of electrical contacts including package electrical contacts and two capacitor electrical contacts;
conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer; and
a solder mask layer over the second conductive layer, the solder mask layer forming electrical contact openings adjacent the package electrical contacts and forming a capacitor opening over the two capacitor electrical contacts; and

mounting a capacitor on the two capacitor electrical contacts to electrically connect the capacitor to the two capacitor electrical contacts with a recessed portion of the capacitor being within the capacitor opening between the two capacitor electrical contacts and a board-side surface of the solder mask layer, wherein mounting the capacitor on the two capacitor electrical contacts includes reflowing solder paste between capacitor terminals of the capacitor and the two capacitor electrical contacts to form direct solder connections with the capacitor terminals and the two capacitor electrical contacts separated only by a capillary flow of the direct solder connections.

2. The method of claim 1 , further comprising:
applying the solder mask layer over the second conductive layer; and
patterning the solder mask layer to form the electrical contact openings adjacent each of the package electrical contacts and forming the capacitor opening over the two capacitor electrical contacts such that the electrical contact openings are solder mask layer defined, and the two capacitor electrical contacts are non solder mask layer defined.

3. The method of claim 2 , further comprising applying pre-solder within the electrical contact openings, but not the capacitor opening.

4. The method of claim 1 , wherein mounting the semiconductor die on the multilayer substrate includes processing a set of solder bumps to form electrical connections between the semiconductor die and the first set of electrical contacts.

5. The method of claim 1 , further comprising applying a plurality of solder bumps to the electrical contact openings to form a solder ball array.

6. A method of forming a semiconductor package comprising:
mounting a semiconductor die on a multilayer substrate, wherein the multilayer substrate comprises:
a dielectric layer;
a first conductive layer forming a first set of electrical contacts on a first side of the dielectric layer;
a second conductive layer forming a second set of electrical contacts on a second side of the dielectric layer, the second set of electrical contacts including package electrical contacts and two capacitor electrical contacts;
conductive vias extending through the dielectric layer between the first conductive layer and the second conductive layer; and
a solder mask layer over the second conductive layer, the solder mask layer forming electrical contact openings adjacent the package electrical contacts and forming a capacitor opening over the two capacitor electrical contacts; and

mounting a capacitor on the two capacitor electrical contacts that includes reflowing solder paste between capacitor terminals of the capacitor and the two capacitor electrical contacts to form direct solder connections with the capacitor terminals.

7. The method of claim 6 , wherein mounting the capacitor includes electrically connecting the capacitor to the two capacitor electrical contacts with a recessed portion of the capacitor being within the capacitor opening between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

8. The method of claim 6 , wherein the capacitor opening has a rounded shape with a radius at least 50 percent of a thickness of the solder mask layer.

9. The method of claim 6 , wherein mounting the semiconductor die on the multilayer substrate is to electrically connect the semiconductor die to the first set of electrical contacts of the multilayer substrate.

10. A method of forming a semiconductor package comprising:
mounting a semiconductor die on a multilayer substrate, wherein the multilayer substrate comprises:
a dielectric layer;
a first conductive layer forming a first set of electrical contacts on a first side of the dielectric layer;
a second conductive layer forming a second set of electrical contacts on a second side of the dielectric layer, the second set of electrical contacts including package electrical contacts and two capacitor electrical contacts;
conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer; and
a solder mask layer over the second conductive layer, the solder mask layer forming electrical contact openings adjacent the package electrical contacts and forming a capacitor opening over the two capacitor electrical contacts; and

mounting a capacitor on the two capacitor electrical contacts, wherein direct solder connections electrically connect the two capacitor electrical contacts with the capacitor terminals.

11. The method of claim 10 , wherein mounting the capacitor includes electrically connecting the capacitor to the two capacitor electrical contacts with a recessed portion of the capacitor being within the capacitor opening between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

12. The method of claim 10 , wherein the capacitor opening has a rounded shape with a radius at least 50 percent of a thickness of the solder mask layer.

13. The method of claim 10 , wherein mounting the semiconductor die on the multilayer substrate is to electrically connect the semiconductor die to the first set of electrical contacts of the multilayer substrate.

14. The method of claim 10 further comprising applying a plurality of solder bumps to the electrical contact openings to form a solder ball array.

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Sinha Snehamay

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title