Multilevel package substrate with stair shaped substrate traces

Patent metadata

Field	Value
Publication number	US-12266597-B2
Application number	US-202117563403-A
Country	US
Kind code	B2
Filing date	Dec 28, 2021
Priority date	Dec 28, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

An electronic device includes a multilevel package substrate with first and second levels, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, and the first level including a second trace layer with a stair shaped second conductive trace feature, the second conductive trace feature having a first portion with a first thickness, and a second portion, having a second thickness greater than the first thickness.

First claim

What is claimed is:

1. An electronic device, comprising:
a multilevel package substrate having a first level and a second level, the first level extending in a first plane of orthogonal first and second directions, the second level extending in a second plane of the first and second directions, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, the first level on the second level and including a second trace layer with a second conductive trace feature, the second conductive trace feature having a first portion and a second portion, the first portion having a first thickness along a third direction, the third direction orthogonal to the first and second directions, the second portion having a side and a second thickness along the third direction, wherein the side of the second portion faces away from the first plane, and the second thickness is greater than the first thickness; and
a die having a conductive terminal electrically coupled to the side of the second portion, wherein the second portion of the second conductive trace feature locates within selective areas of the first level and the selective areas are along a periphery of the die.

2. The electronic device of claim 1 , wherein:
the multilevel package substrate includes a core dielectric layer, a third level, and a fourth level;
the core dielectric layer has opposite first and second sides;
the second level on the first side of the core dielectric layer;
the third level on the second side of the core dielectric layer and extending in a third plane of the first and second directions, the third level including a third trace layer with a third conductive trace feature, a conductive second via that contacts the third conductive trace feature, and a third second dielectric layer;
the fourth level on the third level and extending in a fourth plane of the first and second directions, the fourth level including a fourth trace layer with a fourth conductive trace feature having a second side that faces away from the fourth plane; and
a solder ball attached to the second side of the fourth conductive trace feature.

3. The electronic device of claim 2 , wherein the fourth conductive trace feature has a first portion and a second portion, the first portion of the fourth conductive trace feature having a third thickness along the third direction, the second portion of the fourth conductive trace feature having the second side of the fourth conductive trace feature, the second portion of the fourth conductive trace feature having a fourth thickness along the third direction, and the fourth thickness greater than the third thickness.

4. The electronic device of claim 3 , wherein:
the first thickness is 10 to 20 μm;
the second thickness is 5 to 15 μm greater than the first thickness;
the third thickness is 10 to 20 μm; and
the fourth thickness is 5 to 15 μm greater than the third thickness.

5. The electronic device of claim 3 , wherein:
the selective areas of the first level comprise a first region of the first level proximate a lateral side of the die; and
the fourth conductive trace feature is positioned in a second region of the fourth level.

6. The electronic device of claim 5 , wherein the first region of the first level is under the die.

7. The electronic device of claim 3 , wherein:
the first level includes multiple second conductive trace features, each having respective first and second portions, the respective first portions having the first thickness along the third direction, and the respective second portions having the second thickness along the third direction; and
the fourth level includes multiple fourth conductive trace features, each having respective first and second portions, the respective first portions of the fourth conductive trace features having the third thickness along the third direction, and the respective second portions of the fourth conductive trace features having the fourth thickness along the third direction.

8. The electronic device of claim 1 , wherein:
the first thickness is 10 to 20 μm; and
the second thickness is 5 to 15 μm greater than the first thickness.

9. The electronic device of claim 1 , wherein the selective areas of the first level comprise a first region of the first level proximate a lateral side of the die.

10. The electronic device of claim 1 , wherein the first level includes multiple second conductive trace features, each having respective first and second portions, the respective first portions having the first thickness along the third direction, and the respective second portions having the second thickness along the third direction.

11. A multilevel package substrate, comprising:
a first level that extends in a first plane of orthogonal first and second directions; and
a second level that extends in a second plane of the first and second directions;
the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer; and
the first level on the second level and including a second trace layer with a second conductive trace feature, the second conductive trace feature having a first portion and a second portion, the first portion having a first thickness along a third direction, the third direction orthogonal to the first and second directions, the second portion having a side and a second thickness along the third direction, wherein the side of the second portion faces away from the first plane, and the second thickness is greater than the first thickness, and wherein the second portion of the second conductive trace feature locates within selective areas of the first level and the selective areas are along a periphery of a die attached to the multilevel package substrate.

12. The multilevel package substrate of claim 11 , further comprising a core dielectric layer, a third level, and a fourth level; wherein:
the core dielectric layer has opposite first and second sides;
the second level on the first side of the core dielectric layer;
the third level on the second side of the core dielectric layer and extending in a third plane of the first and second directions, the third level including a third trace layer with a third conductive trace feature, a conductive second via that contacts the third conductive trace feature, and a second dielectric layer;
the fourth level on the third level and extending in a fourth plane of the first and second directions, the fourth level including a fourth trace layer with a fourth conductive trace feature having a second side that faces away from the fourth plane; and
a solder ball attached to the second side of the fourth conductive trace feature.

13. The multilevel package substrate of claim 12 , wherein the fourth conductive trace feature has a first portion and a second portion, the first portion of the fourth conductive trace feature having a third thickness along the third direction, the second portion of the fourth conductive trace feature having the second side of the fourth conductive trace feature, the second portion of the fourth conductive trace feature having a fourth thickness along the third direction, and the fourth thickness greater than the third thickness.

14. The multilevel package substrate of claim 13 , wherein:
the first thickness is 10 to 20 μm;
the second thickness is 5 to 15 μm greater than the first thickness;
the third thickness is 10 to 20 μm; and
the fourth thickness is 5 to 15 μm grea

Assignees

• Texas Instruments Inc

Inventors

• Williamson Jaimal Mallory
• Lo Chun Ping
• Suzuki Yutaka

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title