Fin field effect transistor devices with self-aligned gates
US-11183389-B2 · Nov 23, 2021 · US
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Sieg Stuart A patents
Sieg Stuart A is listed as an inventor on 103 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sieg Stuart A |
| Total patents | 103 |
| First publication | May 28, 2015 |
| Latest publication | Nov 23, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Alternating hardmasks for tight-pitch line formation
US-11171002-B2 · Nov 9, 2021 · US
Alternating hardmasks for tight-pitch line formation
US-2021335619-A1 · Oct 28, 2021 · US
Tunable hardmask for overlayer metrology contrast
US-11121024-B2 · Sep 14, 2021 · US
Alternating hardmasks for tight-pitch line formation
US-11031248-B2 · Jun 8, 2021 · US
Fin cut profile using fin base liner
US-10985025-B2 · Apr 20, 2021 · US
Vertical transport devices with greater density through modified well shapes
US-10943911-B2 · Mar 9, 2021 · US
Measuring and modeling material planarization performance
US-10832919-B2 · Nov 10, 2020 · US
Vertical transistors having multiple gate thicknesses for optimizing performance and device density
US-10811508-B2 · Oct 20, 2020 · US
Vertical transistors having multiple gate thicknesses for optimizing performance and device density
US-10811507-B2 · Oct 20, 2020 · US
Recent patents
Latest publications not already listed above.
Fin field effect transistor devices with self-aligned gates
US-2020294803-A1 · Sep 17, 2020 · US
Alternating hardmasks for tight-pitch line formation
US-2020266066-A1 · Aug 20, 2020 · US
Controlling fin hardmask cut profile using a sacrificial epitaxial structure
US-10741452-B2 · Aug 11, 2020 · US
Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows
US-10734372-B2 · Aug 4, 2020 · US
Controlling gate length of vertical transistors
US-10665715-B2 · May 26, 2020 · US
Semiconductor Fin Length Variability Control
US-2020144069-A1 · May 7, 2020 · US
Verifying planarization performance using electrical measures
US-10642950-B2 · May 5, 2020 · US
Fin cut profile using fin base liner
US-2020135484-A1 · Apr 30, 2020 · US
Controlling fin hardmask cut profile using a sacrificial epitaxial structure
US-2020135570-A1 · Apr 30, 2020 · US
Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices
US-10629489-B2 · Apr 21, 2020 · US
Tunable hardmask for overlayer metrology contrast
US-10622248-B2 · Apr 14, 2020 · US
Approach to prevent collapse of high aspect ratio fin structures for vertical transport fin field effect transistor devices
US-2020098639-A1 · Mar 26, 2020 · US
Controlling gate length of vertical transistors
US-2020075761-A1 · Mar 5, 2020 · US
Alternating hardmasks for tight-pitch line formation
US-10580652-B2 · Mar 3, 2020 · US
Alternating hard mask for tight-pitch fin formation
US-2020066520-A1 · Feb 27, 2020 · US
Semiconductor fin length variability control
US-10535529-B2 · Jan 14, 2020 · US
Semiconductor Fin Length Variability Control
US-2019371613-A1 · Dec 5, 2019 · US
Tunable hardmask for overlayer metrology contrast
US-2019371651-A1 · Dec 5, 2019 · US
Inverse tone direct print euv lithography enabled by selective material deposition
US-2019355625-A1 · Nov 21, 2019 · US
Alternating hardmasks for tight-pitch line formation
US-2019333774-A1 · Oct 31, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 98 |
| Tessera Inc | 5 |
| Globalfoundries Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 69 |
| H10D84/0158 | 54 |
| H10D30/024 | 53 |
| H10P50/695 | 51 |
| H01L29/66795 | 40 |