Tunable hardmask for overlayer metrology contrast

Patent metadata

Field	Value
Publication number	US-10622248-B2
Application number	US-201815861774-A
Country	US
Kind code	B2
Filing date	Jan 4, 2018
Priority date	Jan 4, 2018
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

First claim

What is claimed is:

1. A method of improving overlay metrology contrast, the method comprising:
forming at least one alignment feature in a dielectric oxide layer;
removing a portion of the dielectric oxide layer;
depositing an amorphous silicon layer on the dielectric oxide layer corresponding to the removed portion, wherein the amorphous silicon layer has an extinction coefficient (k) of less than about 0.4 at a wavelength of 633 nm; and
depositing a multilayer patterning stack overlaying the amorphous silicon layer, wherein the transmission of visible light from the multilayer patterning stack to the alignment feature is increased relative to not removing the portion of the dielectric oxide layer and depositing the amorphous silicon layer.

2. The method of claim 1 , wherein the multilayer patterning stack comprises an organic planarizing layer, a hardmask on the organic planarizing layer, and a photoresist on the hardmask layer.

3. The method of claim 1 , wherein the amorphous silicon layer has a refractive index of less than about 4.1.

4. The method of claim 1 , wherein depositing the amorphous silicon layer comprises a vapor deposition process from a gas mixture comprising silane and optionally hydrogen at a temperature within a range of about 30° C. to about 600° C. and a pressure within a range of about 0.1 Torr to about 10 Torr.

5. The method of claim 4 , wherein the hydrogen gas is greater than 10 mol % of the gas mixture and further reduces the extinction coefficient k value within a range from about 0.09 to about 0.03 and a refractive index value within a range of about 3.5 to about 3.2.

6. The method of claim 1 , wherein the amorphous silicon has an extinction coefficient (k) within a range of about 0.09 to about 0.03 at a wavelength of 633 nm.

7. The method of claim 1 , wherein depositing the amorphous silicon layer comprises a vapor deposition process from a gas mixture comprising silane at a temperature within a range of about 30° C. to about 600° C. and a pressure within a range of about 0.1 Torr to about 10 Torr to form the amorphous silicon layer; and doping the amorphous silicon layer with hydrogen to reduce the k value of the amorphous silicon within a range of about 0.4 to about 0.03 at a wavelength of 633 nm.

8. A method of improving overlay metrology contrast, the method comprising:
forming at least one alignment feature in a dielectric oxide layer;
depositing an amorphous silicon layer on the dielectric oxide layer, wherein the amorphous silicon layer is tuned to minimize reflection and maximize transmission by providing an extinction coefficient (k) of less than 0.4 and a refractive index (n) less than about 4.1 at a wavelength of 633 nm; and
depositing a multilayer patterning stack on the tuned amorphous silicon layer, wherein the transmission of visible light from the multilayer patterning stack to the alignment feature is increased relative to not depositing the amorphous silicon layer.

9. The method of claim 8 , wherein the multilayer patterning stack comprises an organic planarizing layer, a hardmask on the organic planarizing layer, and a photoresist on the hardmask layer.

10. The method of claim 8 , wherein the amorphous silicon layer has a thickness within a range from about 5 nanometers to about 10 nanometers.

11. The method of claim 8 , wherein depositing the amorphous silicon layer comprises a vapor deposition process from a gas mixture comprising silane and hydrogen gas at a temperature within a range of about 30° C. to about 600° C. and a pressure within a range of about 0.1 Torr to about 10 Torr.

12. The method of claim 11 , wherein the hydrogen gas is greater than 10 mol % of the gas mixture and further reduces the extinction coefficient k value to within a range from about 0.09 to about 0.03 and the refractive index value to within a range of about 3.5 to about 3.2.

13. The method of claim 8 , wherein the multilayer patterning stack further comprises an adhesion layer, an antireflective layer or a combination thereof.

14. The method of claim 8 , wherein the photoresist is sensitive to deep-ultraviolet (DUV) radiation, extreme ultraviolet (EUV), or mid-ultraviolet (MUV) radiation.

15. A method for tuning an amorphous silicon layer, the method comprising:
depositing an amorphous silicon layer under a multilayer patterning stack, wherein depositing the amorphous silicon layer comprises adjusting a hydrogen content in the amorphous silicon layer to reduce an extinction coefficient (k) value to less than about 0.4 and a refractive index (n) to less than about 4.1 at a wavelength of about 633 nm.

16. The method of claim 15 , wherein adjusting the hydrogen content reduces the extinction coefficient (k) value to within a range from about 0.09 to about 0.03 at a wavelength of about 633 nm and reduces the refractive index (n) to about 3.5 to about 3.2.

17. The method of claim 15 , wherein the multilayer patterning stack comprises, from bottom to top, an organic planarizing layer, a hardmask on the organic planarizing layer, and a photoresist on the hardmask layer.

18. The method of claim 15 , the multilayer patterning stack further comprises an adhesion layer, an antireflective layer or a combination thereof.

19. The method of claim 15 , wherein depositing the amorphous silicon layer comprises a vapor deposition process selected from the group consisting of chemical vapor deposition, plasma enhanced chemical vapor deposition, and plasma vapor deposition from a silane gas.

20. The method of claim 15 , wherein depositing the amorphous silicon layer comprises a vapor deposition process from a gas mixture comprising a silane gas and a hydrogen gas at a temperature within a range of about 30° C. to about 600° C. and a pressure within a range of about 0.1 Torr to about 10 Torr.

Assignees

• IBM

Inventors

• De Silva Ekmini A
• Felix Nelson
• Seshadri Indira
• Sieg Stuart A

Classifications

• G03F9/7076

  Mark details, e.g. phase grating mark, temporary mark · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• G03F9/7084

  Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G03F7/70633

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title