Measuring and modeling material planarization performance

Patent metadata

Field	Value
Publication number	US-10832919-B2
Application number	US-201815950628-A
Country	US
Kind code	B2
Filing date	Apr 11, 2018
Priority date	Apr 11, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

First claim

What is claimed is:

1. A method for modeling planarization performance of a given material of a semiconductor structure comprising:
patterning, using a first mask, a first photoresist layer over a first material deposited over a top surface of a substrate, the first mask defining two or more different design macros to be patterned in two or more different regions of the first photoresist layer;
etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising the two or more different design macros in the two or more different regions;
coating the given material over the patterned topography of the first material;
patterning, using a second mask, a second photoresist layer over the given material, the second mask defining a metrology feature for measuring a critical dimension in each of the two or more different regions;
measuring the critical dimension of the metrology feature in each of the two or more different regions; and
utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material;
wherein the model of the planarization performance is utilizable for modeling formation of the semiconductor structure;
wherein the model of the planarization performance of the given material is further generated based at least in part on an anchor curve that relates measured critical dimensions of metrology features for a same design topography formed with different focus settings of a lithographic patterning tool in multiple regions; and
wherein patterning the first photoresist layer and the second photoresist layer utilizes a same focus setting for the lithographic processing tool, the same focus setting corresponding to a designated point of the anchor curve having a minimal critical dimension, and wherein building the model of the planarization performance comprises measuring an offset of a minimal critical dimension of the metrology feature in each of the two or more different regions to the designated point of the anchor curve.

2. The method of claim 1 , wherein the substrate comprises silicon, the first material comprises at least one of silicon and silicon oxide, and the given material comprises a spin-coated organic layer.

3. The method of claim 1 , wherein each of the two or more different design macros comprises an inside design surrounded by an outside design.

4. The method of claim 3 , wherein each of the inside design and the outside design comprises a pattern of one or more features, the one or more features comprising at least one of: a solid or blank design; a lines and spaces design; and a pillars and holes design.

5. The method of claim 4 , wherein the two or more different design macros have varying densities of the one or more features in the inside design and the outside design.

6. The method of claim 4 , wherein the two or more different design macros have varying sizes of the inside design and the outside design.

7. The method of claim 4 , wherein the two or more different design macros have varying heights of the one or more features in the inside design and outside design.

8. The method of claim 1 , wherein at least one of patterning the first photoresist layer and patterning the second photoresist layer utilizes an extreme ultra violet patterning tool.

9. A method for modeling planarization performance of a given material of a semiconductor structure comprising:
patterning, using a first mask, a first photoresist layer over a first material deposited over a top surface of a substrate, the first mask defining a given design macro to be patterned in each of two or more different regions of the first photoresist layer;
etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising the given design macro in each of the two or more different regions;
coating the given material over the patterned topography of the first material;
patterning, using a second mask, a second photoresist layer over the given material using different focus settings for a lithographic processing tool, the second mask defining a metrology feature for measuring a critical dimension of the given design macro in each of the two or more different regions;
measuring the critical dimension of the metrology feature in each of the two or more different regions; and
generating an anchor curve relating the measured critical dimensions of the metrology feature with the different focus settings for the two or more different regions;
wherein the anchor curve is used to model planarization performance of the given material;
wherein the model of the planarization performance is utilizable for modeling formation of the semiconductor structure;
wherein the anchor curve is generated by forming the given design macro topography with different focus settings for the lithographic processing tool in each of the two or more different regions; and
building the model of the planarization performance comprises patterning additional design macros in the topography of the first material in one or more additional regions of the substrate utilizing a same focus setting for the lithographic processing tool, the same focus setting corresponding to a designated point of the anchor curve having a minimal critical dimension, and measuring an offset of a minimal critical dimension of the metrology feature in the at least one additional region to the designated point of the anchor curve.

10. The method of claim 9 , wherein patterning the additional design macros comprises:
patterning, using a third mask, a third photoresist layer over the first material deposited over the top surface of an additional portion of the substrate, the third mask defining at least one of the additional design macros to be patterned in at least one of the one or more additional regions of the third photoresist layer using the same focus setting corresponding to the minimal critical dimension of the designated point of the anchor curve;
etching portions of the first material exposed by the patterned third photoresist layer to create a patterned topography of the first material comprising the at least one additional design macro in the at least one additional region;
coating the given material over the patterned topography of the first material in the at least one additional region;
patterning a fourth photoresist layer, using the second mask, over the given material in the at least one additional region; and
measuring a minimum of the critical dimension of the metrology feature formed over the additional design macro in the at least one additional region.

11. The method of claim 10 , further comprising relating an offset in the minimum of the critical dimension of the metrology feature formed in at least one additional region to the minimal critical dimension of the designated point of the anchor curve to build the model characterizing the planarization performance of the given material.

12. The method of claim 10 , wherein the additional region of the first material is formed on a different substrate.

13. The method of claim 9 , wherein patterning the additional design macros comprises:
patterning, using a third mask, a third photoresist layer over the first material deposited over the top surface of the substrate, the third mask defining at least one of the additional design macros to be patterned in at least one of the one or more additiona

Assignees

• IBM

Inventors

• Lallement Romain
• Sieg Stuart A

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P95/066 Primary

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title