Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows

Patent metadata

Field	Value
Publication number	US-10734372-B2
Application number	US-201815923683-A
Country	US
Kind code	B2
Filing date	Mar 16, 2018
Priority date	Mar 16, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a vertical transport static random-access memory (SRAM) cell comprising a first active region and a second active region;
the first active region and the second active region being linearly arranged in first and second rows, respectively;
the first row of the first active region comprising a first pull-up transistor, a first pull-down transistor and a first pass gate transistor;
the second row of the second active region comprising a second pull-up transistor, a second pull-down transistor and a second pass gate transistor;
wherein the first active region comprises a first common bottom source/drain region, the first common bottom source/drain region comprising a first p-doped portion, a first n-doped portion adjacent a first edge of the first p-doped portion providing a first p-n junction, and a second n-doped portion adjacent a second edge of the first p-doped portion providing a second p-n junction;
wherein the second active region comprises a second common bottom source/drain region, the second common bottom source/drain region comprising a second p-doped portion, a third n-doped portion adjacent a first edge of the second p-doped portion providing a third p-n junction, and a fourth n-doped portion adjacent a second edge of the second p-doped portion providing a fourth p-n junction;
wherein a first gate region of the first active region extends orthogonal from a first portion of the first row corresponding to the first p-doped portion of the first common bottom source/drain region to a second portion of the second row corresponding to the third p-n junction between the second p-doped portion and the third n-doped portion of the second common bottom source/drain region of the second active region; and
wherein a second gate region of the second active region extends orthogonal from a third portion of the second row corresponding to the second p-doped portion of the second bottom source/drain region to a fourth portion of the first row corresponding to the second p-n junction between the first p-doped portion and the second n-doped portion of the first common bottom source/drain region of the first active region.

2. The semiconductor structure of claim 1 , wherein the first pull-up transistor, the first pull-down transistor and the first pass gate transistor of the first active region share the first common bottom source/drain region.

3. The semiconductor structure of claim 2 , wherein the second pull-up transistor, the second pull-down transistor and the second pass gate transistor of the second active region share the second common bottom source/drain region.

4. The semiconductor structure of claim 3 , wherein the first gate region provides a first gate strap electrical connection between the first gate region and the second active region.

5. The semiconductor structure of claim 4 , wherein the second gate region provides a second gate strap electrical connection between the second gate region and the first active region.

6. The semiconductor structure of claim 5 , wherein the first pull-up transistor and the second pull-up transistor comprise p-type field-effect transistors (PFETs) and the first pull-down transistor, the second pull-down transistor, the first pass gate transistor and the second pass gate transistor comprise n-type field-effect transistors (NFETs).

7. The semiconductor structure of claim 6 , wherein the first gate strap electrical connection between the first gate region and the second active region is at a boundary between the NFET second pass gate transistor and the PFET second pull-up transistor.

8. The semiconductor structure of claim 6 , wherein the first gate strap electrical connection is self-aligned to the first gate region.

9. The semiconductor structure of claim 6 , wherein the second gate strap electrical connection between the second gate region and the first active region is at a boundary between the NFET first pass gate transistor and the PFET first pull-up transistor.

10. The semiconductor structure of claim 1 , further comprising a first contact to the first pass gate transistor and a second contact to the second pass gate transistor.

11. The semiconductor structure of claim 10 , wherein at least one of the first contact and the second contact comprises a shared contact with an adjacent SRAM cell.

12. The semiconductor structure of claim 1 , wherein the first p-n junction in the first row is laterally offset from the third p-n junction in the second row.

13. The semiconductor structure of claim 1 , wherein the second p-n junction in the first row is laterally offset from the fourth p-n junction in the second row.

14. The semiconductor structure of claim 1 , wherein the first pull-up transistor in the first row is laterally offset from the second pull-up transistor in the second row.

15. An integrated circuit comprising:
a vertical transport static random-access memory (SRAM) device comprising one or more SRAM cells;
a given one of the SRAM cells comprising a first active region and a second active region;
the first active region and the second active region being linearly arranged in first and second rows, respectively;
the first row of the first active region comprising a first pull-up transistor, a first pull-down transistor and a first pass gate transistor;
the second row of the second active region comprising a second pull-up transistor, a second pull-down transistor and a second pass gate transistor;
wherein the first active region comprises a first common bottom source/drain region, the first common bottom source/drain region comprising a first p-doped portion, a first n-doped portion adjacent a first edge of the first p-doped portion providing a first p-n junction, and a second n-doped portion adjacent a second edge of the first p-doped portion providing a second p-n junction;
wherein the second active region comprises a second common bottom source/drain region, the second common bottom source/drain region comprising a second p-doped portion, a third n-doped portion adjacent a first edge of the second p-doped portion providing a third p-n junction, and a fourth n-doped portion adjacent a second edge of the second p-doped portion providing a fourth p-n junction;
wherein a first gate region of the first active region extends orthogonal from a first portion of the first row corresponding to the first p-doped portion of the first common bottom source/drain region to a second portion of the second row corresponding to the third p-n junction between the second p-doped portion and the third n-doped portion of the second common bottom source/drain region of the second active region; and
wherein a second gate region of the second active region extends orthogonal from a third portion of the second row corresponding to the second p-doped portion of the second bottom source/drain region to a fourth portion of the first row corresponding to the second p-n junction between the first p-doped portion and the second n-doped portion of the first common bottom source/drain region of the first active region.

16. The integrated circuit of claim 15 , wherein the first pull-up transistor, the first pull-down transistor and the first pass gate transistor of the first active region share the first common bottom source/drain region and the second pull-up transistor, the second pull-down transistor and the second pass gate transistor of the second active region share the second common bottom source/drain region.

17. The integrated circuit of claim 16 , wherein the first gate region provides a

Assignees

• IBM

Inventors

• Anderson Brent A
• Sieg Stuart A
• Wang Junli

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D84/0195

  the components including vertical IGFETs · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title