Fin field effect transistor devices with self-aligned gates

Patent metadata

Field	Value
Publication number	US-11183389-B2
Application number	US-201916353641-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Mar 14, 2019
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

First claim

What is claimed is:

1. A method of forming adjacent fin field effect transistor devices, comprising:
forming at least two vertical fins in a column on a substrate;
depositing a gate dielectric layer on the at least two vertical fins;
depositing a work function material layer on the gate dielectric layer;
depositing a protective liner on the work function material layer;
forming a fill layer on the protective liner;
removing a portion of the fill layer to form an opening between an adjacent pair of the at least two vertical fins, wherein the opening exposes a portion of the protective liner;
depositing an etch-stop layer on exposed surfaces of the fill layer and the exposed portion of the protective liner;
forming a gauge layer on the etch-stop layer in the opening to a predetermined height including a portion of the etch-stop layer exposed above a top surface of the gauge layer; and
removing the exposed portion of the etch-stop layer to form an etch-stop segment in the opening; and
removing the gauge layer from the etch stop segment.

2. The method of claim 1 , further comprising, removing the fill layer, wherein the gauge layer and fill layer are removed with a single etch.

3. The method of claim 2 , further comprising, removing portions of the protective liner, portions of the work function material layer, and portions of the gate dielectric layer.

4. The method of claim 3 , further comprising, forming a top source/drain on each of the adjacent pair of the at least two vertical fins.

5. The method of claim 4 , further comprising, forming an interlayer dielectric layer on the substrate.

6. The method of claim 4 , wherein the etch-stop layer is a dielectric material selected from the group consisting of silicon oxide (SiO), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbo-oxynitride (SiCON), silicon boro carbonitride (SiBCN), and combinations thereof.

7. The method of claim 4 , wherein the adjacent pair of the at least two vertical fins are separated by a gap with a width in a range of about 20 nanometers (nm) to about 200 nm.

8. The method of claim 4 , wherein the protective liner has a thickness in a range of about 2 nanometers (nm) to about 20 nm.

9. The method of claim 4 , wherein the protective liner is dielectric material selected from the group consisting of silicon boro carbonitride (SiBCN), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbo-oxynitride (SiCON), and combinations thereof.

10. A method of forming adjacent fin field effect transistor devices, comprising:
forming at least two vertical fins in a column on a substrate;
forming a source/drain region below each of the at least two vertical fins;
forming a bottom spacer layer on the substrate;
depositing a gate dielectric layer on the at least two vertical fins and bottom spacer layer;
depositing a work function material layer on the gate dielectric layer;
depositing a dielectric protective liner on the work function material layer;
forming a fill layer on the protective liner;
removing a portion of the fill layer to form an opening between an adjacent pair of the at least two vertical fins, wherein the opening exposes a portion of the protective liner;
depositing an etch-stop layer on the exposed surfaces of the fill layer and the exposed portion of the protective liner;
forming a gauge layer on the etch-stop layer in the opening to a predetermined height including a portion of the etch-stop layer exposed above a top surface of the gauge layer;
removing the exposed portion of the etch-stop layer to form an etch-stop segment in the opening; and
forming a top source/drain on a top surface of each of the adjacent pair of the at least two vertical fins.

11. The method of claim 10 , wherein the adjacent pair of the at least two vertical fins are separated by a gap with a width in a range of about 20 nanometers (nm) to about 200 nm.

12. The method of claim 10 , wherein the etch-stop layer is a dielectric material selected from the group consisting of silicon oxide (SiO), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbo-oxynitride (SiCON), silicon boro carbonitride (SiBCN), and combinations thereof.

13. The method of claim 10 , wherein the protective liner is a dielectric material selected from the group consisting of silicon boro carbonitride (SiBCN), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbo-oxynitride (SiCON), and combinations thereof.

14. The method of claim 10 , wherein the etch-stop layer can have a thickness in a range of about 2 nm to about 20 nm.

15. A method of forming adjacent fin field effect transistor devices, comprising:
depositing a gate dielectric layer on at least two vertical fins aligned in a column;
depositing a work function material layer on the gate dielectric layer;
depositing a protective liner on the work function material layer, wherein the protective liner is made of amorphous silica (a-Si) or a dielectric material;
forming a dielectric fill layer on the protective liner;
removing a portion of the dielectric fill layer to form an opening between an adjacent pair of the at least two vertical fins, wherein the opening exposes a portion of the protective liner;
depositing an etch-stop layer on exposed surfaces of the fill layer and the exposed portion of the protective liner; and
forming a dielectric gauge layer on the etch-stop layer in the opening to a predetermined height including a portion of the etch-stop layer exposed above a top surface of the gauge layer.

16. The method of claim 15 , wherein the etch-stop layer covers a step between the protective liner and the fill layer.

17. The method of claim 15 , further comprising removing the exposed portion of the etch-stop layer to form an etch-stop segment in the opening.

18. The method of claim 17 , wherein the dielectric gauge layer and the dielectric fill layer are made of the same dielectric material.

19. The method of claim 18 , wherein the dielectric gauge layer and the dielectric fill layer are removed with a single etch.

20. The method of claim 17 , further comprising removing the dielectric gauge layer from the etch stop segment, and removing portions of the dielectric protective liner, work function layer, and gate dielectric layer from the at least two vertical fins aligned in a column.

Assignees

• IBM

Inventors

• Xu Wenyu
• Sieg Stuart A
• Xie Ruilong
• Sporre John R

Classifications

• H10P50/267

  using plasmas · CPC title

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title