Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Patent metadata

Field	Value
Publication number	US-10811508-B2
Application number	US-201715803918-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	Sep 20, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

First claim

What is claimed is:

1. A method of forming a configuration of semiconductor devices, the method comprising:
forming a plurality of performance-based circuits comprising a plurality of first transistors formed over a performance region of a major surface of a substrate;
where each of the plurality of first transistors comprises:
a first channel fin structure; and
a first gate structure along at least a portion of a sidewall surface of the first channel fin structure;
where the first gate structure comprises a first gate thickness dimension; and

forming a plurality of density-based circuits comprising a plurality of second transistors formed over a density region of the major surface of the substrate, where the plurality of density-based circuits includes a number of repetitive density-based circuits;
where each of the plurality of second transistors comprises:
a second channel fin structure; and
a second gate structure along at least a portion of a sidewall surface of the second channel fin structure;
where the second gate structure comprises a second gate thickness dimension that is less than the first gate thickness dimension;

where the repetitive density-based circuits are configured to compensate for a failure rate of the plurality of density-based circuits;
where each of the plurality of first transistors comprises a first vertical field effect (VFET) transistor having a first fin-shaped VFET channel and a first VFET gate:
where the first channel fin structure comprises the first fin-shaped VFET channel;
where the first channel gate structure comprises the first VFET gate;
where each of the plurality of second transistors comprises a second VFET transistor having a second fin-shaped VFET channel and a second VFET gate:
where the second channel fin structure comprises the second fin-shaped VFET channel; and
where the second gate structure comprises the second VFET gate.

2. The method of claim 1 , where forming the first gate structure comprises forming the first gate structure such that the first gate thickness dimension comprises an initial first gate thickness dimension.

3. The method of claim 2 , where:
forming the first gate structure further comprises forming a first gate spacer over the first gate structure;
the first gate spacer comprises a first gate spacer thickness dimension;
the first gate spacer thickness dimension is substantially the same as the first gate thickness dimension; and
forming the first gate structure further comprises applying an etch operation that is selective to the first gate structure over the first gate spacer to reduce the initial first gate thickness dimension to the first gate spacer thickness dimension.

4. The method of claim 3 , where forming the second gate structure comprises forming the second gate structure such that the second gate thickness dimension comprises an initial second gate thickness dimension.

5. The method of claim 4 , where forming the second gate structure further comprises forming a second gate spacer over the second gate structure.

6. The method of claim 5 , where:
the second gate spacer comprises a second gate spacer thickness dimension; and
the second gate spacer thickness dimension is substantially the same as the second gate thickness dimension.

7. The method of claim 6 , where forming the second gate structure further comprises applying an etch operation that is selective to the second gate structure over the second gate spacer to reduce the initial second gate thickness dimension to the second gate spacer thickness dimension.

8. The method of claim 7 , where the same fabrication operation is used to form the first channel fin structure and the second channel fin structure.

9. The method of claim 8 , where the same fabrication operation is used to form the first gate structure and the second gate structure.

10. The method of claim 7 , where forming the second gate spacer further comprises:
providing the second gate spacer with an initial second gate spacer thickness dimension that is substantially the same as the first gate spacer thickness dimension; and
reducing the initial second gate spacer thickness dimension to the second gate spacer thickness dimension.

11. A method of forming a configuration of semiconductor devices, the method comprising:
forming a plurality of first channel fin structures over a performance region of a major surface of a substrate;
forming a plurality of second channel fin structures over a density region of the major surface of the substrate, where the plurality of second channel fin structures includes a number of repetitive second channel fin structures;
forming a plurality of first gate structures comprising forming a first gate structure along at least a portion of a sidewall surface of each of the plurality of first channel fin structures, where the first gate structure comprises a first gate thickness dimension; and
forming a plurality of second gate structures comprising forming a second gate structure along at least a portion of a sidewall surface of each of the plurality of second channel fin structures, where the second gate structure comprises a second gate thickness dimension that is less than the first gate thickness dimension;
where the repetitive second channel fin structures are configured to compensate for a failure rate of the plurality of second gate structures;
where each of the plurality of first channel fin structures comprises a first fin-shaped vertical field effect transistor (VFET) channel;
where each of the plurality of second channel fin structures comprises a second fin-shaped VFET channel;
where each of the plurality of first gate structures comprises a first VFET gate; and
where each of the plurality of second gate structures comprises a second VFET gate.

12. The method of claim 11 , where:
a first gate pitch dimension comprises a distance from a selected location on the first gate structure of any one of the plurality of first gate structures to a corresponding point on the first gate structure of an adjacent one of the plurality of first gate structures;
a second gate pitch dimension comprises a distance from a selected location on the second gate structure of any one of the plurality of second gate structures to a corresponding point on the second gate structure of an adjacent one of the plurality of second gate structures; and
the second gate pitch dimension is less than the first gate pitch dimension.

Assignees

• IBM

Inventors

• Anderson Brent A
• Lie Fee Li
• Sieg Stuart A
• Wang Junli

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title