Verifying planarization performance using electrical measures

Patent metadata

Field	Value
Publication number	US-10642950-B2
Application number	US-201815889415-A
Country	US
Kind code	B2
Filing date	Feb 6, 2018
Priority date	Feb 6, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

First claim

What is claimed is:

1. A computer-implemented method for verifying planarization performance using electrical measures, the computer-implemented method comprising:
modeling, using a processor, a planarization layer for a topography of a device;
designing a chip including one or more structures of a design;
measuring electrical characteristics of the one or more structures, wherein the electrical characteristics include a threshold voltage of each of the one or more structures;
receiving target specification for the one or more structures;
comparing measured electrical characteristics of the one or more structures to the target specifications for the one or more structures;
applying the planarization model to the one or more structures;
correlating the measured electrical characteristics to the planarization model; and
modifying a process for fabricating the chip based at least in part on a result of the correlation.

2. The computer-implemented method of claim 1 , wherein the modeling includes:
varying a depth-of-focus to measure a critical dimension of a known structure;
determining a reference curve for the known structure;
measuring a critical dimension of the one or more structures of the design; and
comparing the measured critical dimension of the one or more structures to the determined reference curve for the known structure.

3. The computer-implemented method of claim 2 , wherein comparing includes:
fitting a critical dimension for each of the one or more structures on the reference curve; and
determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

4. The computer-implemented method of claim 2 , wherein comparing includes:
determining a curve for each of the one or more structures of the design; and
comparing each curve for each of the one or more structures to the reference curve.

5. The computer-implemented method of claim 1 , wherein the measuring includes measuring a gate length of each of the one or more structures.

6. The computer-implemented method of claim 1 , wherein the measuring includes measuring metal height of each of the one or more structures.

7. The computer-implemented method of claim 1 , wherein the planarization layer is an organic planarization layer.

8. A system for verifying planarization performance using electrical measures, the system comprising:
storage medium, the storage medium being communicatively coupled to a processor;
the processor configured to:
model a planarization layer for a topography of a device;
design a chip including one or more structures;
collect measured electrical characteristics of the one or more structures wherein the electrical characteristics include a threshold voltage of each of the one or more structures;
compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures;
apply the planarization model to the one or more structures;
correlate the measured electrical characteristics to the planarization layer; and
modify a process for fabricating the chip based at least in part on a result of the correlation.

9. The system of claim 8 , wherein the modeling includes varying a depth-of-focus to measure a critical dimension of a known structure;
determining a reference curve for the known structure;
measuring a critical dimension of the one or more structures; and
comparing the measured critical dimension of the one or more structures of the design to the determined reference curve for the known structure.

10. The system of claim 9 , wherein comparing includes fitting a critical dimension for each of the one or more structures on the reference curve; and
determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

11. The system of claim 9 , wherein the comparing includes determining a curve for each of the one or more structures of the design; and
comparing each curve for each of the one or more structures to the reference curve.

12. The system of claim 8 , wherein the planarization layer is an organic planarization layer.

13. A computer program product for verifying planarization performance using electrical measurements, the computer program product comprising:
a computer readable storage medium having stored thereon program instructions executable by a processor to cause the processor to:
model a planarization layer for a topography of a device;
design a chip including one or more structures;
collect measured electrical characteristics of the one or more structures wherein the electrical characteristics include a threshold voltage of each of the one or more structures;
compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures;
apply the planarization model to the one or more structures;
correlate the measured electrical characteristics to the planarization layer; and
modify a process for fabricating the chip based at least in part on a result of the correlation.

14. The computer program product of claim 13 , wherein the modeling includes varying a depth-of-focus to measure a critical dimension of a known structure;
determining a reference curve for the known structure;
measuring a critical dimension of the one or more structures of the design; and
comparing the measured critical dimension of the one or more structures to the determined reference curve for the known structure.

15. The computer program product of claim 14 , wherein comparing includes fitting a critical dimension for each of the one or more structures on the reference curve; and
determining a focal plane offset to the reference curve based at least in part on the critical dimension of each of the one or more structures.

16. The computer program product of claim 14 , wherein the comparing includes determining a curve for each of the one or more structures; and
comparing each curve for each of the one or more structures to the reference curve.

Assignees

• IBM

Inventors

• Lallement Romain
• Sieg Stuart A

Classifications

• H10P74/00

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title